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The stability, leakage power and speed of Static random access memory (SRAM) have become an important issue with CMOS technology scaling. In this paper, a controller circuit is introduced which is separately controlling the load, driver and access transistors of SRAM cell. Based on word line signal value, optimal body bias voltage is generated through control circuitry to control stability, leakage and speed in SRAM cell. The proposed cell gives faster read and writes with an improvement of 68.5% and 89.2% over conventional 6T SRAM cell. In standby mode, about 62.2% leakage power reduction is observed in $8\times 16$ array architecture of SRAM. The proposed cell is implemented with 65nm CMOS technology and exhibits higher hold and write margins with an improvement of 26.29% in hold margin and 16.6% improvement in write margin as compared to conventional 6T SRAM cell. Robustness of the proposed SRAM cell with respect to stability, leakage and speed are confirmed under process, voltage and temperature variations.

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32nm CNTFET model is applied for circuit simulations.

The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.