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In this paper, four baseband chain architectures used in multistandard (UMTS–WLAN) reconfigurable receivers will be introduced, simulated and, compared. The architectures are realized using 0.25 μm CMOS technology operating with 1.2 V supply voltage. The baseband chain consists of three stages: the first and the last stage are programmable gain amplifiers and the intermediate stage is an active Gm-RC LPF filter. The proposed architectures are compared in terms of DC-gain, noise, linearity, SFDR, and power consumption. The best receiver architecture is then derived based on system level analysis and based on a defined figure-of-merit. The best baseband chain bandwidth is controlled by the active G_m-RC filter with a value 2.2 MHz for UMTS and 11 MHz for WLAN. The baseband gain can be programmed in the range of -6÷68 dB, while the input-referred noise density is less 20 nV/√Hz for UMTS and 25 μV/√Hz for WLAN.

A new simple dual-output second generation current conveyor (DO-CCII) circuit is proposed. Designed in a standard 0.5-μm CMOS process, the circuit operates at ±1.5 V supply voltages with a total power consumption of 106 nW. Main characteristics of the proposed DO-CCII are its simplicity, small silicon area consumption, and not suffering from the body effect of MOS transistors. The proposed circuit is employed to implement a first-order low-pass filter with upper -3 dB cut-off frequency of as low as 3.2 Hz.

A proposal of a fractional ($1+\alpha$)-order low-pass filter is presented in this paper. The proposed filter operates in the current-mode and it is designed using Multi-Output Current Followers (MO-CFs), Dual-Output Current Follower (DO-CF), Dual-Output Adjustable Current Amplifier (DO-ACA) and Adjustable Current Amplifiers (ACAs) as active elements within the presented topology of the filter. The filter possesses ability to electronically control its order and also the pole frequency by changing the current gain of current amplifiers (ACAs) already present in the structure. Three different values of the order and pole frequency of the proposed low-pass filter were tested as an example. Design of the proposed filter is supported by simulation and experimental results. Simulations of the circuit are carried out in PSPICE simulator with behavioral models of used active elements. The experimental laboratory measurements are performed with the help of available devices forming equivalent circuits. Simulations and experimental results of the electronical control of the order and pole frequency are compared in this contribution.

In this paper, a new active-C filter realizing the general $n$th-order low-pass voltage transfer functions using $n$ voltage differencing gain amplifiers (VDGAs) is presented. In this realization minimum number of equal-valued grounded capacitors and $n$ active elements are used. Due to the adjustability of the transconductance of the VDGA with current, different gains can be realized using the same building block and a simple filter structure can be created. The filter which is composed of VDGA building blocks is suitable for integration and advantageous in terms of eliminating parasitic effects because all capacitors are grounded and the filter structure has no resistors. All simulations are performed on SPICE and the accuracy of this method is validated experimentally with commercially available products upon on-board circuit.

Deep submicron CMOS technology proves to be suitable for transceiver design at mmwave band frequencies. At the same time, it has been a challenging task to obtain high performance at mmwave frequencies. In this paper, a 28GHz low-IF receiver frontend with improved performance by incorporating a proposed linear Gm-C low-pass filter (LPF) is presented using 40nm CMOS technology targeting for 5G wireless system. A mathematical expression for the linearity of the proposed filter is derived and compared with the basic filter model. The improved linearity (IIP3 of $-7.18$dBm) of the proposed filter results in the enhancement of linearity and hence the Figure of Merit (FOM) of the receiver with the proposed filter. The receiver attains a conversion gain of 34.6dB, a noise figure of 3.1dB and IIP3 of $-21.7$dBm. The total current drawn by the receiver is 27.3mA at a 1.2V power supply. The overall FOM of the receiver with the proposed filter is improved to 0.30 whereas the FOM of the receiver with the basic filter model is 0.13. The area of the receiver is $770\ast 380\mu {\mathrm{\text{m}}}^2$ whereas the proposed filter occupies $27.7\ast 21.9\mu {\mathrm{\text{m}}}^2$.

A current-mode first-order filter configuration simultaneously providing noninverting and inverting low-pass (LP) and high-pass (HP) responses depending on passive element choice is proposed. In addition, all-pass filter (APF) responses can be easily obtained with interconnection of LP and HP output currents. The proposed filter employs only two differential voltage current conveyors, a grounded resistor and a grounded capacitor, so it is suitable for integrated circuit realization. It provides the feature of high output impedance. It does not need any passive element matching constraints. A voltage-mode oscillator based on the inverting APF is presented as a typical application. The performance of the proposed configuration is verified through many SPICE simulation and experimental test results.

A fractional low-pass filter operating in a low-frequency range is necessary for the filtering of biomedical signals. Thus, we propose a fractional low-pass filter of order ($1+\alpha$) which is implemented using a current follower transconductance amplifier (CFTA). The presented structure is compact. It comprises of five CFTAs along with three grounded capacitors and two resistors. Additionally, this filter structure can be electronically tuned for its order and frequency variation, and these tunings are independent of each other. This electronic tuning is established through the bias current of the active component used. The layout of the proposed filter was designed in Cadence Virtuoso, covering 7920$\mu$m² of chip area. It is operating at ±900mV with a power consumption of 6.8mW. In the simulation results, both pre-layout and post-layout results are included, which indicates that the design is appropriate for fabrication. To check robustness, PVT analysis, Monte-Carlo analysis and THD are also performed. The proposed circuit has also been tested through experiment and its results are also presented. The proposed filter is used to implement a Leaky-Integrate-and-Fire neuron model.

A new universal active filter configuration is presented in this paper which is capable of realizing all three first-order filter responses namely all pass (AP), low pass (LP) and high pass (HP) using a single second generation voltage conveyor (VCII+), a virtually grounded capacitor and two resistors. The proposed circuit offers tunability of the cut-off frequency, gain (for HP filter) and simultaneous availability of two filter outputs, one at a low impedance node (HP/AP), the other output, namely the LPF will require a voltage buffer to avoid loading. The nonideal analysis of filter responses based on the nonideal model of VCII+ is carried out by considering all the parasitic immittances and nonideal gains and found that they have no significant effect on the performance of the proposed filter structure. Sensitivity analysis with respect to active and passive components has also been carried out. The functionality of the presented circuit has been validated through simulations and experimental results, where the VCII+ was implemented using the macro model of the commercially available CFOA IC AD844. Additionally, the proposed circuit has been tested using a CMOS VCII+ implemented with 0.18$\mu$m TSMC technology parameters. The tests include advanced evaluations based on Monte Carlo simulations.

Bridge influence lines can reflect the performance status of bridge structures and are an important tool to evaluate high-speed railway bridges. Because a high-speed train can cause large dynamic response on a bridge, it is difficult to identify the static influence line of the bridge. To extract the static bridge influence lines for bridge evaluation, this paper proposes a low-pass filter design method for static influence line identification. By maximizing the difference in bridge static and dynamic energy, the relationship between the frequency domain characteristics of the bridge dynamic response and the filter parameters is established. Based on this relationship, reasonable values of the low-pass filter parameters can be determined. After filtering the dynamic response, the quasi-static response can be effectively obtained, and the bridge static influence line can be identified through the least square regularization method. Finally, a numerical example of the vehicle–bridge interaction model is used to verify the effectiveness of the proposed method. The results show that the low-pass filter designed through the proposed principle can accurately remove the dynamic effects, and its stability and robustness are good. The research results provide a reliable method for the static influence line identification of high-speed railway bridges.

Graph convolutional networks (GCNs) have achieved great success on graph-structured data. Many GCNs can be considered low-pass filters for graph signals. In this paper, we propose a more powerful GCN, named BiGCN, that extends to bidirectional filtering. Specifically, we consider the original graph structure information and the latent correlation between features. Thus BiGCN can filter the signals along with both the original graph and a latent feature-connection graph. Compared with most existing GCNs, BiGCN is more robust and has powerful capacities for feature denoising. We perform node classification and link prediction in citation networks and co-purchase networks with three settings: Noise-Rate, Noise-Level, and Structure-Mistakes. Extensive experimental results demonstrate that our model outperforms the state-of-the-art graph neural networks in both clean and artificially noisy data.