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A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90nm 1.2V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009$\mu {\mathrm{\text{m}}}^2$, a worst case delay of 858ps, and a power consumption of 898uW at 1G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600$\mu {\mathrm{\text{m}}}^2$) of the total comparator area and contributes 54% (484$\mu$W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.

To improve conversion efficiency and output quality of the energy harvester, a novel interface circuit with composite maximum power point tracking (MPPT) in energy harvesting applications is proposed in this paper. By using the ultra-low-voltage multiplier with digital control and simple one-cycle variable frequency technique, the converter realizes fast power tracking and high conversion efficiency, and minimizes the power consumption and harmonics, thereby obtaining high tracking precise and low total harmonic distortion (THD). Implemented in 65-nm CMOS process, this converter achieves 85.9% peak power efficiency with dc output voltage of 1.6V. The peak tracking efficiency and THD are 99.2% and 1.3%, respectively. The peak output power is 18.31$\mu$W, and the power loss of the entire converter is only 16.53$\mu$W.

As the key component of wireless network-on-chip (WiNoC), wireless router is required to handle a large number of data packets which could cause network congestion. The congestion not only reduces the network performance, but also results in additional power consumption. In this paper, a low-power WiNoC with congestion-aware wireless node is proposed. Firstly, flit counter unit and address resolution unit are added in wireless interface (WI), which can sense the congestion information and destination address information of each wireless node dynamically. Secondly, through the proposed congestion judgment algorithm, the congestion judgment unit in global network can judge the priority of each wireless node pair and set the highest-priority wireless node pair to use the channel resources preferentially. The mechanism can effectively alleviate the congestion of wireless nodes and ensure the stability of system performance. In addition, a sleep mechanism is utilized to switch off WI which fails in the wireless channel competition. Experimental results show that the proposed scheme can effectively improve the performance in terms of packets’ transmission latency and network throughput.

A new design technique is proposed and discussed for the design of active load using the bulk-driven method. The proposed method uses gate-driven input drivers with bulk-driven MOS load. Further, it is used to design single stage amplifiers, such as common source (CS) and common gate (CG). In addition to the proposed technique, a very efficient method is implemented to improve and control the gain of the amplifiers, which is named as Gain Control by Bulk Amplification (GACOBA) Technique. The large signal, small signal and frequency domain analysis of proposed designs are done and to verify the outcomes it is simulated in SPECTER at 0.7V supply with 45nm CMOS technology. The result shows that the transconductance and gain of proposed single stage CS amplifier are increased without affecting impedance seen by output node. On the other hand, GACOBA technique is useful for gain enhancement in CS and CG amplifier.

Proposed work presents an OR-XNOR-based thermal-aware synthesis approach to reduce peak temperature by eliminating local hotspots within a densely packed integrated circuit. Tremendous increase in package density at sub-nanometer technology leads to high power-density that generates high temperature and creates hotspots. A nonexhaustive meta-heuristic algorithm named nondominated sorting genetic algorithm-II (NSGA-II) has been employed for selecting suitable input polarity of mixed polarity dual Reed–Muller (MPDRM) expansion function to reduce the power-density. A parallel tabular technique is used for input polarity conversion from Product-of-Sum (POS) to MPDRM function. Without performance degradation, the proposed MPDRM approach shows more than 50% improvement in the area and power savings and around 6% peak temperature reduction for the MCNC benchmark circuits than that of earlier literature at the logic level. Algorithmic optimized circuit decompositions are implemented in physical design domain using CADENCE INNOVUS and HotSpot tool and silicon area, power consumption and absolute temperature are reported to validate the proposed technique.

This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit analysis. Post-layout simulation results of the proposed clock generator in 180nm CMOS technology are also presented. It exhibits a wide tuning range of 807 MHz to 2.66 GHz. The phase noise of the output signal is about $-111$dBc/Hz at 10MHz offset frequency. Frequency changes less than $113.06\mathrm{\text{ppm}}{∕}^{\circ }\mathrm{\text{C}}$ in the temperature range of $-40^{\circ }$C–$100^{\circ }$C. The clock generator consumes 0.657mW of power. Results show improvement in comparison to the previous works.

In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18$\mu$m CMOS process. The designed LNA shows a gain of 15.28dB, NF of 0.376dB, the power dissipation of 936$\mu$W and IIP3 of $-4.36$dBm at 2.4GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3mW${}^{-1}$ and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.

In this paper, a low-power structure as an inverter-base circuit is reported for broadband applications. The focus in this study is in obtaining a low-power structure. By applying cascoded structure to an inverter as a feedforward network in the structure, the DC current and hence the power dissipation are decreased. Also, by adding a two-stage active feedback, which yields no miller capacitance, to the cascoded inverter, the structure of the TIA is completed. Simulation results in HSPICE using 90nm CMOS technology parameters show 41dB$\mathrm{\Omega }$ transimpedance gain, 6.5GHz frequency bandwidth and 2.7$\mu$Arms input referred noise, which consumes only 1.67mw power at 1V supply. Results and analysis indicate that the proposed TIA is suitable to work as a low-power 10 Gbps transimpedance amplifier in an optical receiver.

With the emergence of the internet-of-things (IoT), many devices process data through the IEEE 802.11 wireless networks. To satisfy the increased data processing, the wireless fidelity (Wi-Fi) networks must have sufficient capacity. IEEE 802.11ax is formulated to provide higher data processing capabilities for IoT applications. The IEEE 802.11ax receiver operating at 5GHz must be able to withstand interference from nearby IoT applications. Hence, the low-noise amplifier (LNA) employed in such receivers must have a high input-referred third-order intercept point (IIP3). This paper aims to present a wideband LNA operating at 5GHz with high IIP3 for modern IoT transceivers using IEEE 802.11ax protocol. The LNA is designed and implemented in UMC 65nm CMOS technology using the Cadence virtuoso design tool. The proposed LNA can provide a maximum gain of 17.64dB while consuming 8.18mW of power from a 1.2V supply. It can be noted that the minimum noise figure (NF) achieved is 3.67dB and the corresponding IIP3 is 9.44dBm at 5GHz from the pre-layout simulations.

Most image processing applications are naturally imprecise and can tolerate computational error up to a specific limit. In such applications, savings in power are achieved by pruning the data path units, such as an adder module. Truncation, however, may lead to errors in computing, and therefore, it is always a challenge between the amount of error that can be tolerated in an application and savings achieved in area, power and delay. This paper proposes a segmented approximate adder to reduce the computation complexity in error-resilient image processing applications. The sub-carry generator aids in achieving a faster design while carry speculation method employed improves the accuracy. Synthesis results indicate a reduced die-area up to 36.6%, improvement in delay up to 62.9%, and reduction in power consumption up to 34.1% compared to similar work published previously. Finally, the proposed adder is evaluated by using image smoothing and sharpening techniques. Simulations carried out on these applications prove that the proposed adder obtains better peak signal-to-noise ratio than those available in the literature.

Static random access memory (SRAM) is a sort of RAM where information is not permanently stored and does not require routine updating. To reduce leakage power without sacrificing performance, a variety of approaches have been applied to SRAM cells. In this study, we suggest a new 16T SRAM design that can function in active, park, standby, or hold modes. A fully static mode of operation for SRAM is made possible by the 16T SRAM structure, which also enhances write margin (WM) and removes charging conflict between devices during read and write operations. The key objectives of the suggested architecture are to retain logic state in park mode while maintaining stability and reducing standby time in active mode, as well as to reduce leakage current in standby mode. This is done by removing feedback from the back-to-back inverters during write operations via the data-dependent supply block. This makes it possible for the suggested bitcell to considerably increase the WM. A novel SRAM cell with 16 transistors is created with subthreshold operation and enhanced data stability. By using an equalized bit line technique to avoid leakage due to enhanced data pattern and RBL detection, the suggested single-ended SRAM cell with dynamic feedback control lowers the static noise margin for ultra-low power transfer. A sleep transistor is incorporated into the architecture to save power consumption when the system is in standby mode due to inefficient voltage transmission. Tanner EDA tool V.14.1 on 45-nm CMOS was used for design and simulation. The outcomes demonstrate a considerable decrease in no-load current and power loss.

This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a $3\times 3$ kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the $3\times 3$ kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., $G_H$ and $G_V$, respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient $(G)$ of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing $G_H$ and $G_V$ cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window.

Media processing applications can tolerate error up to a certain limit due to the perceptual limitations of the human eye. Since adders are ubiquitous in power-hungry media processing applications, they can be approximated without much compromise in quality. An adder with better error characteristics without significant compromise in area and power is required to meet the future demands of ever-increasing computational needs. In order to achieve the same, a novel segmentation technique has been proposed. By varying the number of bits in each segment, three different designs are proposed, each with its advantage. Each proposed adder is segmented into three portions, namely Most Significant Portion (MSP), Intermediate Significant Portion (ISP) and Least Significant Portion (LSP). The sub-adder’s sum in each portion is computed concurrently to reduce the critical path delay.

The proposed heterogeneous adder (HEAD) designs achieve better accuracy than the state-of-the-art designs. Synthesis results show that HEAD consumes less area up to 41.8% and consumes less power ranging from 0.8% to 51%, than existing adders. Exhaustive simulations are carried out on benchmarking image sharpening application to prove that the proposed adders obtain a better quality-effort tradeoff than the existing designs.

A wearable system based on MEMS technology has been envisioned to address the need for the detection of falls in the elderly. This paper presents the development of a low-power micro-machined threshold accelerometer (alternatively known as the G-switch) which is designed for use as impact sensors in fall detection. A surface micromachining process (PolyMUMPs) was chosen for the fabrication of initial prototypes and the design of the G-switch is discussed.

Currently, static circuit power is becoming a major concern, dominating the total power consumption due to the scaling down of CMOS technology. The smaller sizes drastically affect the leakage current, which integrated circuit designers attempt to overcome this issue. Hence, several methods and technologies have been proposed to prevail this phenomenon. One of these methods is using memory structures in logic designs. A Hybrid MTJ/CMOS circuit is one of these promising techniques to design low-power nonvolatile circuits with power gating ability and low overhead for reconfigurable possibilities. In this paper, we have proposed a fully nonvolatile, low-power Full-Adder based on MTJs that uses the spin transfer torque method assisted by the spin hall effect. Simulation results of these designs by HSPICE show that they can work fast with low-power consumption compared to other state-of-the-art nonvolatile full-adders.

In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.

A low-power and low-data-rate (100 kbps) fully integrated CMOS impulse radio ultra-wideband (IR-UWB) transmitter for biomedical application is presented in this paper. The transmitter is designed using a standard 180-nm CMOS technology that operates at the 3.1-5 GHz frequency range with more than 500 MHz of channel bandwidth. Modulation scheme of this transmitter is based on on-off keying (OOK) in which a short pulse represents binary “1” and absence of a pulse represents binary “0” transmission. During the ‘off’ state (sleep mode) the transmitter consumes only 0.4 µW of power for an operating voltage of 1.8 V while during the impulse transmission state it consumes a power of 36.29 µW. A pulse duration of about 3.5 ns and a peak amplitude of the frequency spectrum of about -47.8 dBm/MHz are obtained in the simulation result which fully complies with Federal Communication Commission (FCC) regulation.

Implantable biomedical sensors and continuous real time in vivo monitoring of various physiological parameters requires low-power sensor electronics and wireless telemetry for transmission of sensor data. In this article, generic blocks required for such systems have been demonstrated with design examples. Ideally neural or electro-chemical sensor signal monitoring units comprise of low noise amplifiers, current or voltage mode analog to digital domain data conversion circuits and wireless telemetry circuits. The low-noise amplifier described here has a novel open loop amplifier scheme used for neural signal recording systems. The design has been implemented using 0.5-μm SOIBiCMOS process. The fabricated chip can work with 1 V supply and consumes 805 nA. The current mode analog to digital conversion signal processing circuitry takes the current signal as an input and generates a pulse-width modulated data signal. The data signal is then modulated with a high frequency carrier signal to generate FSK data for wireless transmission. The design is fabricated in 0.5-μm standard CMOS process and consumes 1.1 mW of power with 3.5 V supply.

This article has reviewed the development of embedded system, and sketched the system composition and working principle of digital quadrant. According to the current digital quadrant research, design methods about improving measurement precision and reducing the power consumption of the system are summarized, and its future development were discussed.