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This paper presents a novel low-voltage rail-to-rail comparator circuit and derives optimal transistor size ratios for both conventional latch-based and the proposed comparators which operate in transistor subthreshold region. The obtained analytical results serve well as guidelines for designing low-voltage comparators and the proposed circuit is significantly faster than existing rail-to-rail comparator designs in ultra-low voltage operation.

A versatile low-voltage CMOS circuit with a trapezoidal transconductance characteristic and independently programmable slope, height and horizontal position is designed in 0.18$\mu$m standard CMOS technology. The proposed circuit is constructed from combination of two linearization methods to enhance the linearity in low voltage applications. A $-$118dB THD was obtained for a 400mV peak to peak differential input voltage at 125KHz. Simulation results using HSPICE that verify the functionality of circuit with 1.5V supply are presented. The total power consumption is only 120$\mu$W. The circuit can find application in the implementation of membership functions in analogue and mixed-signal neuro-fuzzy systems.

In this paper, a new realization of a current-mode first-order all-pass filter (APF) using a single active building block (ABB) and one grounded capacitor is presented. As the ABB, the current backward transconductance amplifier (CBTA) is used, which is one of the most recently reported active elements in the literature. The theoretical results are in detail verified by numerous SPICE simulations using a new low-voltage implementation of CBTA. In the design, the PTM 90nm level-7 CMOS process BSIM3v3 parameters with $\pm$0.45V supply voltages were used. The proposed resistorless CBTA-C APF provides easy electronic tuning of the pole frequency in the frequency range from 763kHz to 17.6MHz, which is more than one decade. Maximum power dissipation of the circuit is 828$\mu$W at bias current 233$\mu$A. Nonideal, parasitic effects, sensitivity analyses, temperature and noise variation, current swing capability, and Monte Carlo analysis results are also provided. Compared to prior state-of-the-art works, the proposed CBTA-C APF has achieved the highest figure of Merit value, which proves its superior performance.

This paper describes a low-voltage bulk-driven differential CMOS Schmitt trigger with tunable hysteresis for use in noise removal applications. The hysteresis of the proposed Schmitt trigger is designed based on a regenerative current feedback and its width is adjustable by two control voltages. The center of the hysteresis can also be adjusted by either the control voltages or input common-mode voltage. The principle operation of the proposed circuit is discussed, its main formulas are derived and its performance is verified by Cadence post-layout simulations. Designed in the TSMC 0.18$\mu$m standard CMOS process, the circuit consumes $39\times 17.5\mu$m² of silicon area. Post-layout simulation results indicate that the hysteresis width of the Schmitt trigger can be adjusted from 170 to 270mV and the ratio of the hysteresis width variation to supply voltage is 11.11%. Operated with 0.8V supply voltage, the power consumption of the circuit ranges from 0.48 to 1.12mW.

This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7M$\mathrm{\Omega }$, wide bandwidth of 239.245MHz and low power dissipation of 104$\mu$W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.

In this paper, electronic implementation of fractional-order Rössler system using operational transconductance amplifiers (OTAs) is presented which until now was only being investigated through numerical simulations. The realization offers the benefits of low-voltage implementation, integrability and electronic tunability. In addition, the proposed circuit is a MOS only design (as no BJTs have been used) which contains only grounded components and is therefore suitable for monolithic VLSI design. The chaotic behavior of the fractional-order Rössler system in consideration with the incommensurate orders has been demonstrated which finds many applications in several fields. The theoretical predictions of the proposed implementation have been verified through experimentation and HSPICE simulator using Austrian Micro System (AMS) 0.35$\mu$m CMOS process and the obtained results have been found in good agreement with the Matlab simulink theoretical results obtained using FOMCON simulink toolbox. Besides, a secure message communication system has been considered to demonstrate fully the usefulness of the chaotic system.