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The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-off the performance yield and leakage power dissipation in nanoscaled devices. Low threshold voltage improves the device characteristics with large leakage power in nanoscaled devices. Several leakage reduction techniques at different levels are used to mitigate the leakage power dissipation. Lower leakage power increases the reliability by reducing the cooling cost of the portable systems. In this article, we are presenting the explanatory general review of the commonly used leakage reduction techniques at circuit level. We have analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at different technology nodes in active as well as standby modes. Process, voltage and temperature effects are checked for reliability purpose. Our comparative results and discussion of different leakage reduction techniques are very useful to illustrate the effective technique in active and standby modes.

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as used in radio frequency (RF) devices. Multi-threshold CMOS (MTCMOS) is the most used circuit technique to reduce the leakage current in idle circuit. In this paper, different parameters are analyzed on MTCMOS Technique. MTCMOS technique achieves 99.6% reduction of leakage current, active power is reduced by 42.64% and delay is reduced by 71.9% as compared with conventional double gate 14T full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45 nm technology.

The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.