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Compared to multi-valued logic (MVL) with conventional 2-state FETs with a single threshold, MVL computing architectures, based on 4-state SWS (Spatial wavefunction switched) and QDG (quantum dot gate)-FETs having multiple thresholds, results in reduced device count, higher clock (CLK) speed, and lower power consumption. We have experimentally shown multi-state characteristics in SWS-FETs as well as QDG-FETs. This paper presents a novel QDG-SWS-FET that: (1) functions as a multi-bit FET for efficient low-power logic, (2) can be configured as a quantum dot (QD) nonvolatile random access memory (NVRAM), and (3) is suitable for in-memory MVL computing architecture that are compatible with sub-7nm technology nodes. A QDG-SWS-FET with the addition of a control gate dielectric layer functions as a NVRAM cell. Furthermore, it is shown that one single SWS-QD-NVRAM cell gives the functionality of a 1-bit NAND. We have developed circuit/device models and performed quantum simulations for novel multi-layer quantum dot/quantum well FETs and NVRAMs. Our simulations have shown 4-states/2-bit output-input transfer characteristics in SWS-CMOS inverters and NAND gates using two Si/SiGe quantum well channels.

Static random-access memory (SRAM) is an essential component in the architecture of modern microprocessors and VLSI circuits. The problems of high power consumption, large area, circuit complexity, and data stability against noise are among the most important indicators of performance and obstacles to the current use of SRAM. Ternary, quaternary, and higher-order logic (MLV) systems have shown the potential in overcoming these limitations in increasing the information density compared to the traditional binary system. The quantum dot channel field-effect transistor (QDC-FET) and quantum well Spatial Wavefunction Switched field-effect transistor (SWS-FET) are a new alternative with multiple operating states, low power consumption, and smaller footprints. This work presents a new four-state SRAM design that uses SWS-FET and compares it with Voltage-Mode CMOS Quaternary logic design. In addition, this work studies the noise margin in the memory circuit of the quadrilateral logic system and its effect on data stability. Furthermore, this study shows the reliability of quaternary SRAM design by evaluating the impact of errors.

Compared to multi-valued logic (MVL) with conventional 2-state FETs with a single threshold, MVL computing architectures, based on 4-state SWS (Spatial wavefunction switched) and QDG (quantum dot gate)-FETs having multiple thresholds, results in reduced device count, higher clock (CLK) speed, and lower power consumption. We have experimentally shown multi-state characteristics in SWS-FETs as well as QDG-FETs. This paper presents a novel QDG-SWS-FET that: (1) functions as a multi-bit FET for efficient low-power logic, (2) can be configured as a quantum dot (QD) nonvolatile random access memory (NVRAM), and (3) is suitable for in-memory MVL computing architecture that are compatible with sub-7nm technology nodes. A QDG-SWS-FET with the addition of a control gate dielectric layer functions as a NVRAM cell. Furthermore, it is shown that one single SWS-QD-NVRAM cell gives the functionality of a 1-bit NAND. We have developed circuit/device models and performed quantum simulations for novel multi-layer quantum dot/quantum well FETs and NVRAMs. Our simulations have shown 4-states/2-bit output-input transfer characteristics in SWS-CMOS inverters and NAND gates using two Si/SiGe quantum well channels.

Static random-access memory (SRAM) is an essential component in the architecture of modern microprocessors and VLSI circuits. The problems of high power consumption, large area, circuit complexity, and data stability against noise are among the most important indicators of performance and obstacles to the current use of SRAM. Ternary, quaternary, and higher-order logic (MLV) systems have shown the potential in overcoming these limitations in increasing the information density compared to the traditional binary system. The quantum dot channel field-effect transistor (QDC-FET) and quantum well Spatial Wavefunction Switched field-effect transistor (SWS-FET) are a new alternative with multiple operating states, low power consumption, and smaller footprints. This work presents a new four-state SRAM design that uses SWS-FET and compares it with Voltage-Mode CMOS Quaternary logic design. In addition, this work studies the noise margin in the memory circuit of the quadrilateral logic system and its effect on data stability. Furthermore, this study shows the reliability of quaternary SRAM design by evaluating the impact of errors.