Narrow Results

The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high- and low-threshold buffers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an “in situ reliability assessment” of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high- or low-threshold buffers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

The increasing number of clock domain crossings in modern systems-on-chip makes the careful consideration of metastability paramount. However, the manifestation of metastability at a flip-flop output is often unduly reduced to late transitions only, while glitches are hardly ever accounted for. In this paper we study the occurrence of glitches resulting from metastability in detail. To this end we propose a measurement circuit whose principle substantially differs from the conventional approach, and by that allows to reliably detect glitches. By means of experimental measurements on an FPGA target we can clearly identify late transitions, single glitches and double glitches as possible manifestations of metastability. Some of these behaviors are unexpected as they do not follow from the traditional modeling theory. We also study the dependence of metastable behavior on supply voltage. Beyond confirming that, as reported in previous literature, the metastable decay constant $\tau$ is voltage-dependent, we also produce strong evidence that the relative occurrence of glitches is not voltage-dependent.