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This work presents a novel security platform for industrial communications using a nine-MicroBlaze MPSoC. This platform has low power consumption and cost, therefore, it is very appropriate for embedded systems, where restrictions on cost and power consumption have to be fulfilled. This system uses the RSA asymmetric algorithm combined with the AES symmetric algorithm, which was developed using two encryption modes, ECB and CBC. In this way, the platform makes possible to combine different algorithms and modes in function of the necessities of speed and security required. Furthermore, due to the implementation of standard algorithms (AES and RSA) and modes (ECB and CBC), this platform can be connected to the Internet, and can even use secure protocols as SSL.

Networks on Chip (NoCs) are commonly used to integrate complex embedded systems and multiprocessor platforms due to their scalability and versatility. Modeling tools used at the functional level use SystemC to perform hardware–software co-design and error correction concurrently, thus, reducing time to market.

This work analyzes a JPEG encoding algorithm mapped onto a configurable M × N, mesh/torus, NoC platform described in SystemC with the transaction level modeling (TLM) standard; timing constraints for both, the router and network interface controller, are assigned according to a hardware description language (HDL) model written for this purpose. Processing nodes are also described as SystemC threads and their computation delays are assigned depending on the amount and cost of the operations they perform. The programming model employed is message passing.

We start by describing and profiling the JPEG algorithm as a task graph; then, four partitioning proposals are mapped onto three NoCs of different size. Our analysis comprises changes in topology, virtual channel depth, routing algorithms, network speed and task-node assignments. Through several high-level simulations we evaluate the impact of each parameter and we show that, for the proposed model, most improvements come from the algorithm partitioning.

Due to clock and power constraints, it is hard to extract more power out of single core architectures. Thus, multi-core systems are now the architecture of choice to provide the needed computing power. In embedded system, multi-processor system-on-a-chip (MPSoC) is widely used to provide the needed power to effectively run complex embedded applications. However, to effectively utilize an MPSoC system, tools to generate optimized schedules is highly needed. In this paper, we design an integrated approach to task scheduling and memory partitioning of multiple applications utilizing the MPSoC system simultaneously. This is in contrast to the traditional decoupled approach that looks at task scheduling and memory partitioning as two separate problems. Our framework is also based on pipelined scheduling to increase the throughput of the system. Results on different benchmarks show the effectiveness of our techniques.

Even though multi-core systems are effective architectures to overcome the limitation of single-core systems, techniques to improve reliability, throughput and power consumption are highly needed. With the increasing complexity of multi-processor systems-on-a-chip (MPSoCs) to handle the ever increasing complexity of embedded computing applications, the reliability of such systems is now a big concern in the industry. Complex MPSoCs typically have multiple execution modes with different throughput and reliability performances. These complex embedded systems are also expected to perform under minimum power and energy consumptions. In this paper, we present efficient techniques for low-energy and thermal-aware schedules that meet the deadlines under chip reliability constraints. The presented techniques under different objective functions are implemented and executed on multiple embedded applications under multiple underlying system architectures to show the performance and efficiency of the techniques.

In this paper, a novel approach to accelerate parameter extraction process of surface-potential-based (PSP) MOSFET model is presented for the submicron MOS transistor. To reduce the computational time, Field Programmable Gate Array (FPGA) implementation of PSP model library — SiMKit is demonstrated using Xilinx’s Zynq $\mathrm{\text{Ultrascale}}+\mathrm{\text{MPSoC}}$ (Multi-processor System-on-Chip) platform. Parameter extraction is carried out using Particle Swarm Optimization (PSO) algorithm for 65nm technology nMOS devices. With the available measurement data, 32 various PSP model parameters are extracted. Experimental results validate the performance and accuracy of parameter extraction by achieving Root Mean Square Error below 10% for various current–voltage characteristics of nMOS device. 41.57% acceleration in execution time for extraction process is achieved by Zynq $\mathrm{\text{Ultrascale}}+\mathrm{\text{MPSoC}}$ platform compared to the conventional computer-based software approach. In addition, various design optimization directives are explored, and their performances are compared as a part of RTL generation of SiMKit.

Embedded multimedia systems often run multiple time-constrained applications simultaneously. To meet the throughput constraints given in the specification, each application must be provided with enough resources by the underlying architecture, which is generally a multiprocessor system-on-chip (MPSoC). For this purpose, a mechanism for task binding and scheduling is required to provide each application with a timing guarantee, keeping in mind the available resources like processor(s) and memory bandwidth. Commonly, synchronous dataflow graphs (SDFGs) are used to model time-constrained multimedia applications. There are resource allocation strategies for SDFGs that help in formulating efficient techniques for calculating the throughput of a bounded and scheduled SDFG. The strategies are effective in terms of run-time and allocated resources. However, there is no unified modeling technique to simultaneously represent the application and the underlying architecture with resource allocation. This paper discusses a novel modeling technique using Colored Timed Petri Nets (CTPNs), which can be used to model the application as well as the architecture and the resource allocation. Such a representation helps in checking properties like liveness and boundedness for the application, taking into account the resource allocation and thus helping in defining satisfactory schedules for the executable tasks.