Narrow Results

The executions of various complex models reliant on quantum-dot cell automata (QCA) are of high eagerness for investigators. So far, the structure of complex adders in QCA is focused on bringing down clock delay, cell count, and logic gates. This paper proposes the circuit format of a 4-bit multiplier utilizing a carry save adder (CSA) and its implementation on QCA. The CSA is framed with another QCA design of the full adder circuit. The CSA gives preferable expansion strategies over Brent–Kung (BK) adder and Landler–Fisher (LF) adder. This multiplier represents fewer cell counts and clock delays conversely with past designs.