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In-memory computing is an emerging technique to fulfill the fast growing demand for high-performance data processing. This technique provides fast processing and high throughput by accessing data stored in the memory array rather than dealing with complicated operation and data movement on hard drive. For data processing, the most important computation is dot product, which is also the core computation for applications such as deep learning neuron networks, machine learning, etc. As multiplication is the key function in dot product, it is critical to improve its performance and achieve faster memory processing. In this paper, we present a design with the ability to perform in-memory multi-bit multiplications. The proposed design is implemented by using quantum-dot transistors, which enable multi-bit computations in the memory cell. Experimental results demonstrate that the proposed design provides reliable in-memory multi-bit multiplications with high density and high energy efficiency. Statistical analysis is performed using Monte Carlo simulations to investigate the process variations and error effects.

Multiplication plays an important role in digital signal processing. Reducing the power consumption in multipliers will bring significant power reduction to the overall digital system. (7,3) counters are one of the components that are used in parallel multipliers though it is not so popular as the (4:2) compressor. Several (7,3) counters have been reported but most of them are implemented in conventional CMOS style. In this paper, a low power (7,3) counter based on adiabatic switching principles is proposed. HSPICE simulations show that it achieves huge power savings than the static CMOS counterpart.

An original low-power low-voltage multifunctional structure with improved performances will be further presented, allowing to implement (with minor changes in the design) four important functions: the signal gain with theoretical null distortions, voltage multiplying with very good linearity and simulation of a perfect linear resistor with both positive and negative equivalent resistance. The linearity will be strongly increased by implementing original techniques, while the silicon occupied area per function will be reduced as a result of the circuit multifunctionality. The structure is implemented in 0.35 μm CMOS technology and is supplied at ±3 V. The circuit presents a very good linearity (THD < 0.1% for differential amplifier and active resistors and THD < 0.15% for multiplier), correlated with an extended range of the input voltage (-1.5V < v₁ - v₂ < 1.5 V). The tuning range of the active resistor is about 100kΩ – 1.5MΩ. The second-order effects are also considered, being proposed an original technique based on an anti-parallel connection for compensating the linearity degradation introduced by these effects.

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

Elliptic curve cryptosystems (ECC) are becoming more and more popular and are included in many standards, as they offer high security strength when compared with other conventional public-key cryptosystems, for the same key length. But the security strength of hardware implementations of ECC is challenged by side channel attacks (SCA) such as power analysis. Reversible logic circuits ideally consume zero energy, which serves as the motivation to implement cryptographic algorithms against power analysis attacks. This paper proposes two new hardware architectures for performing montgomery multiplication in GF(p) and GF(2^m), as they are the power consuming operations in ECC. The two architectures are optimized to reduce the hardware cost and they are then implemented in reversible logic with reduced number of quantum cost. In this work, the reversible logic synthesis is performed with Toffoli family of reversible gates. The performance metrics of all the multipliers are analyzed and properly tabulated. Scalar multiplication on elliptic curve points, which is the core operation used in every elliptic curve cryptosystem, has been implemented in reversible logic by using the proposed reversible montgomery multipliers.

This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V_DDL, V_DDH) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V_DDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier.

In this paper, a new multiplier using array architecture and a fast carry network tree is presented which uses dynamic CMOS technology. Different reforms are performed in multiplier architecture. In the first step of multiplier operator, a novel radix-16 modified Booth encoder is presented which reduces the number of partial products efficiently. In this research, we present a new algorithm for partial product reduction in multiplication operations. The algorithm is based on the implementation of compressor elements by means of carry network. The structure of these compressors into reduction trees takes advantage of the modified Wallace tree for integration of adder cells and provides an alternative to conventional operator methods. We show several reduction techniques that illustrate the proposed method and describe carry-skip examples that combine dynamic CMOS with classic conventional compressors in order to modify each scheme. In network multiplier, a novel low power high-speed adder cell is presented which uses 14 transistors in its structure. Critical path is minimized to reduce latency in whole operator architecture. Final adder of multiplier uses an optimized carry hybrid adder. The presented final adder network uses dynamic CMOS technology. It sums two final operands in a very efficient way, which has significant effect in operator structure. Presented multiplier reduces latency by 12%, decreases transistor count by 8% and modifies noise problem in an efficient way in comparison with other structures.

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90nm CMOS technology and 0.9V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25dB for image processing; similarly, with a decrease of 0.3dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

A new architecture of 4-bit reversible multiplier with scalability factor of order $4N$ is presented in this paper. The design procedure is based on a unique method of gates placement, which produces parity preserving circuits. This property facilitates graceful testing and full coverage of single-bit faults at lower overhead. The circuit is designed and implemented on the top of reversible analyser for obtaining operating costs in terms of number of wires, gate cost, quantum cost, garbage output and ancilla input. Testable implementation of recently reported multiplier circuits has also been performed using the existing method of testing under the same platform. This work achieved a reduction of up to 33% in operating costs when all the parameters are combined together.

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50nm, 90nm, and 120nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50nm technology consumes 25uW of power at 3.33GHz with 76ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

Modern electronic devices are supported by multicore processors and they have become an unavoidable part of recent technologies. The Arithmetic Logic Unit (ALU) is one of the indispensable parts of the Central Processing Unit (CPU) which performs most of the operations. Operations like multiplications, and exponentials consume more power than other normal operations. Power management is one of the major challenges in designing processors. To maximize speed and reduce power consumption, a new technique in Multiplier and ALU incorporated with a multicore processor has been proposed. The Proposed Approximate Compatible ALU (ACALU) is designed to perform specified operations that consume more power, using an advanced multiplication technique called the First One First Operand (FOFO) method. The selection process of eight bits is done by the FOFO method followed by error detection and error approximation is performed to get the accurate output. The ACALU performs these operations in the Approximate Computing Mode which utilizes only eight bits for the operations, thus reducing the power consumption. The results of several analyses between multipliers, ALUs, and microprocessors are provided. As we optimize the multiplier and ALU unit, the multicore processor is also enhanced. The proposed multicore processor is compared with the AMD processor and the latest INTEL processor and the comparison results show that the proposed technique is 95.2% and 97.8% more efficient than the existing processors. Thus, the power consumption is minimized and the performance speed is increased in the proposed multicore processor.

This paper proposes two novel approaches: a signed–unsigned modified Booth decoder/encoder that is used for the production of partial products and a 5-2 compressor for the addition stage of partial products. The improvement of a circuit can be done at the transistor level and the gate level. To improve the circuits at the gate level for the modified Booth decoder/encoder, a new table was designed and also the 5-2 compressor was obtained by changing the truth table. Speed, power consumption and area were improved in the proposed structures. In this paper, at the transistor level, the gate diffusion input (GDI) technique was used to implement logical gates and the gate-level delay of the GDI structures was also calculated. The results indicated that the proposed 5-2 compressor had a delay of 119 ps with a power consumption of 65$\mu$W, which shows a 23.5% improvement in power delay product (PDP) compared to the best structure in the comparison table, whereas the proposed Booth decoder/encoder had a delay of 257 ps with a power consumption of 61.74$\mu$W and shows a 63.7% improvement in PDP compared to previous studies. By using the proposed structures in the multiplier, a 22% improvement in PDP was observed. To simulate the obtained structures, the TSMC 0.18 and 0.09$\mu$m technologies and the HSPICE software were used. Cadence software was used to implement the layouts of the proposed structures.

In this paper, complete geometric symmetry and conservation law classification of the generalized KdV types of equations are investigated. All of the geometric vector fields and second-order multipliers for the equations are obtained, and the corresponding conservation laws of the equations are presented explicitly. These comprise all of the second-order conservation laws for the equations. Furthermore, an analytic method is developed for dealing with the exact solutions to the generalized nonlinear partial differential equations with composite function terms.

This paper concerns the structural stability of smooth cylindrically symmetric transonic flows in a concentric cylinder. Both cylindrical and axi-symmetric perturbations are considered. The governing system here is of mixed elliptic–hyperbolic and changes type and the suitable formulation of boundary conditions at the boundaries is of great importance. First, we establish the existence and uniqueness of smooth cylindrical transonic spiral solutions with nonzero angular velocity and vorticity which are close to the background transonic flow with small perturbations of the Bernoulli’s function and the entropy at the outer cylinder and the flow angles at both the inner and outer cylinders independent of the symmetric axis, and it is shown that in this case, the sonic points of the flow are nonexceptional and noncharacteristically degenerate, and form a cylindrical surface. Second, we also prove the existence and uniqueness of axi-symmetric smooth transonic rotational flows which are adjacent to the background transonic flow, whose sonic points form an axi-symmetric surface. The key elements in our analysis are to utilize the deformation-curl decomposition for the steady Euler system to deal with the hyperbolicity in subsonic regions and to find an appropriate multiplier for the linearized second-order mixed type equations which are crucial to identify the suitable boundary conditions and to yield the important basic energy estimates.

Constant proportion portfolio insurance (CPPI) strategy is a very popular investment solution which provides an investor with a capital protection as well as allows for an equity market participation. In this paper, we propose a two-step approach to the numerical optimization of the CPPI main parameter, multiplier. First, we identify an admissible range of the multiplier values by controlling the shortfall probability (chosen as a measure of the gap risk). Second, within the admissible range, we choose the optimal multiplier value with respect to the omega ratio (chosen as a performance measure). We illustrate the performance of our optimization algorithm on simulated CPPI paths in the Black–Scholes environment with discrete trading as well as on the historical S&P500 data using the block-bootstrap simulations.

We obtain all Dirichlet spaces ℱ_q, q ∈ ℝ, of holomorphic functions on the unit ball of ℂ^N as weighted symmetric Fock spaces over ℂ^N. We develop the basics of operator theory on these spaces related to shift operators. We do a complete analysis of the effect of q ∈ ℝ in the topics we touch upon. Our approach is concrete and explicit. We use more function theory and reduce many proofs to checking results on diagonal operators on the ℱ_q. We pick out the analytic Hilbert modules from among the ℱ_q. We obtain von Neumann inequalities for row contractions on a Hilbert space with respect to each ℱ_q. We determine the commutants and investigate the almost normality of the shift operators. We prove that the C*-algebras generated by the shift operators on the ℱ_q fit in exact sequences that are in the same Ext class. We identify the groups K₀ and K₁ of the Toeplitz algebras on the ℱ_q arising in K-theory. Radial differential operators are prominent throughout. Some of our results, especially those pertaining to lower negative values of q, are new even for N = 1. Many of our results are valid in the more general weighted symmetric Fock spaces ℱ_b that depend on a weight sequence b.

Let ${𝒜}$ and $𝔄$ be Banach algebras such that ${𝒜}$ is a Banach $𝔄$-bimodule with compatible actions. We define the product ${𝒜}⋊𝔄$, which is a strongly splitting Banach algebra extension of $𝔄$ by ${𝒜}$. After characterization of the multiplier algebra, topological center, (maximal) ideals and spectrum of ${𝒜}⋊𝔄$, we restrict our investigation to the study of semisimplicity, regularity, Arens regularity of ${𝒜}⋊𝔄$ in relation to that of the algebras ${𝒜}$, $𝔄$ and the action of $𝔄$ on ${𝒜}$. We also compute the first cohomology group $H^1({𝒜}⋊𝔄,{({𝒜}⋊𝔄)}^{(n)})$ for all $n\in \mathbb{N}\cup \{0\}$ as well as the first-order cyclic cohomology group $H_{\lambda }^1({𝒜}⋊𝔄,{({𝒜}⋊𝔄)}^{(1)})$, where ${({𝒜}⋊𝔄)}^{(n)}$ is the $n$th dual space of ${𝒜}⋊𝔄$ when $n\in \mathbb{N}$ and ${𝒜}⋊𝔄$ itself when $n=0$. These results are not only of interest in their own right, but also they pave the way for obtaining some new results for Lau products and module extensions of Banach algebras as well as triangular Banach algebra. Finally, special attention is devoted to the cyclic and $n$-weak amenability of ${𝒜}⋊𝔄$. In this context, several open questions arise.

The Bochner–Schoenberg–Eberlein (BSE)-property on commutative Banach algebras is a property related to multiplier algebras of Banach algebras. In this paper, we answer the problem (12) raised by Javanshiri and Nemati in [Amalgamated duplication of the Banach algebra $𝔄$ along a $𝔄$-bimodule ${𝒜}$, J. Algebra Appl. 17(9) (2018) 1850169-1–1850169-21]. In this paper, under certain conditions, we show that the amalgamated Banach algebra ${𝒜}⋊𝔄$ is BSE-algebra if and only if ${𝒜}$ and $𝔄$ are BSE-algebras.