Narrow Results

This paper concerns the structural stability of smooth cylindrically symmetric transonic flows in a concentric cylinder. Both cylindrical and axi-symmetric perturbations are considered. The governing system here is of mixed elliptic–hyperbolic and changes type and the suitable formulation of boundary conditions at the boundaries is of great importance. First, we establish the existence and uniqueness of smooth cylindrical transonic spiral solutions with nonzero angular velocity and vorticity which are close to the background transonic flow with small perturbations of the Bernoulli’s function and the entropy at the outer cylinder and the flow angles at both the inner and outer cylinders independent of the symmetric axis, and it is shown that in this case, the sonic points of the flow are nonexceptional and noncharacteristically degenerate, and form a cylindrical surface. Second, we also prove the existence and uniqueness of axi-symmetric smooth transonic rotational flows which are adjacent to the background transonic flow, whose sonic points form an axi-symmetric surface. The key elements in our analysis are to utilize the deformation-curl decomposition for the steady Euler system to deal with the hyperbolicity in subsonic regions and to find an appropriate multiplier for the linearized second-order mixed type equations which are crucial to identify the suitable boundary conditions and to yield the important basic energy estimates.

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25dB for image processing; similarly, with a decrease of 0.3dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

Let ${𝒜}$ and $𝔄$ be Banach algebras such that ${𝒜}$ is a Banach $𝔄$-bimodule with compatible actions. We define the product ${𝒜}⋊𝔄$, which is a strongly splitting Banach algebra extension of $𝔄$ by ${𝒜}$. After characterization of the multiplier algebra, topological center, (maximal) ideals and spectrum of ${𝒜}⋊𝔄$, we restrict our investigation to the study of semisimplicity, regularity, Arens regularity of ${𝒜}⋊𝔄$ in relation to that of the algebras ${𝒜}$, $𝔄$ and the action of $𝔄$ on ${𝒜}$. We also compute the first cohomology group $H^1({𝒜}⋊𝔄,{({𝒜}⋊𝔄)}^{(n)})$ for all $n\in \mathbb{N}\cup \{0\}$ as well as the first-order cyclic cohomology group $H_{\lambda }^1({𝒜}⋊𝔄,{({𝒜}⋊𝔄)}^{(1)})$, where ${({𝒜}⋊𝔄)}^{(n)}$ is the $n$th dual space of ${𝒜}⋊𝔄$ when $n\in \mathbb{N}$ and ${𝒜}⋊𝔄$ itself when $n=0$. These results are not only of interest in their own right, but also they pave the way for obtaining some new results for Lau products and module extensions of Banach algebras as well as triangular Banach algebra. Finally, special attention is devoted to the cyclic and $n$-weak amenability of ${𝒜}⋊𝔄$. In this context, several open questions arise.

The 4-2 compressor has been widely employed in the design of multipliers. The considerable impact of 4-2 compressors on the efficiency of multipliers has created significant research interests in design of new compressor structures. In the vast range of error resilient applications, multiplication plays an important role in performing computation. Imprecise (approximate) realization of multiplication results in considerable area, power and delay efficiency at the cost of negligible computational errors. In this paper, an imprecise 4-2 compressor is presented. Spintronic devices as promising alternative technologies for silicon-based FET are considered for implementation of the proposed design. All designs are simulated exhaustively at the circuit level and application level. The conducted simulations indicate the superiority of the proposed design compared with the related state-of-the-art in all aspects. The proposed design has more than two and three times lower power and power delay product, respectively, compared to the best previous design.

In this paper, we introduce and characterize controlled dual frames in Hilbert spaces. We also investigate the relation between bounds of controlled frames and their related frames. Then, we define the concept of approximate duality for controlled frames in Hilbert spaces. Next, we introduce multiplier operators of controlled frames in Hilbert spaces and investigate some of their properties. Finally, we show that the inverse of a controlled multiplier operator is also a controlled multiplier operator under some mild conditions.

An original low-power low-voltage multifunctional structure with improved performances will be further presented, allowing to implement (with minor changes in the design) four important functions: the signal gain with theoretical null distortions, voltage multiplying with very good linearity and simulation of a perfect linear resistor with both positive and negative equivalent resistance. The linearity will be strongly increased by implementing original techniques, while the silicon occupied area per function will be reduced as a result of the circuit multifunctionality. The structure is implemented in 0.35 μm CMOS technology and is supplied at ±3 V. The circuit presents a very good linearity (THD < 0.1% for differential amplifier and active resistors and THD < 0.15% for multiplier), correlated with an extended range of the input voltage (-1.5V < v₁ - v₂ < 1.5 V). The tuning range of the active resistor is about 100kΩ – 1.5MΩ. The second-order effects are also considered, being proposed an original technique based on an anti-parallel connection for compensating the linearity degradation introduced by these effects.

A new architecture of 4-bit reversible multiplier with scalability factor of order $4N$ is presented in this paper. The design procedure is based on a unique method of gates placement, which produces parity preserving circuits. This property facilitates graceful testing and full coverage of single-bit faults at lower overhead. The circuit is designed and implemented on the top of reversible analyser for obtaining operating costs in terms of number of wires, gate cost, quantum cost, garbage output and ancilla input. Testable implementation of recently reported multiplier circuits has also been performed using the existing method of testing under the same platform. This work achieved a reduction of up to 33% in operating costs when all the parameters are combined together.

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50nm, 90nm, and 120nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50nm technology consumes 25uW of power at 3.33GHz with 76ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

Constant proportion portfolio insurance (CPPI) strategy is a very popular investment solution which provides an investor with a capital protection as well as allows for an equity market participation. In this paper, we propose a two-step approach to the numerical optimization of the CPPI main parameter, multiplier. First, we identify an admissible range of the multiplier values by controlling the shortfall probability (chosen as a measure of the gap risk). Second, within the admissible range, we choose the optimal multiplier value with respect to the omega ratio (chosen as a performance measure). We illustrate the performance of our optimization algorithm on simulated CPPI paths in the Black–Scholes environment with discrete trading as well as on the historical S&P500 data using the block-bootstrap simulations.

The Bochner–Schoenberg–Eberlein (BSE)-property on commutative Banach algebras is a property related to multiplier algebras of Banach algebras. In this paper, we answer the problem (12) raised by Javanshiri and Nemati in [Amalgamated duplication of the Banach algebra $𝔄$ along a $𝔄$-bimodule ${𝒜}$, J. Algebra Appl. 17(9) (2018) 1850169-1–1850169-21]. In this paper, under certain conditions, we show that the amalgamated Banach algebra ${𝒜}⋊𝔄$ is BSE-algebra if and only if ${𝒜}$ and $𝔄$ are BSE-algebras.

The executions of various complex models reliant on quantum-dot cell automata (QCA) are of high eagerness for investigators. So far, the structure of complex adders in QCA is focused on bringing down clock delay, cell count, and logic gates. This paper proposes the circuit format of a 4-bit multiplier utilizing a carry save adder (CSA) and its implementation on QCA. The CSA is framed with another QCA design of the full adder circuit. The CSA gives preferable expansion strategies over Brent–Kung (BK) adder and Landler–Fisher (LF) adder. This multiplier represents fewer cell counts and clock delays conversely with past designs.

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

Modern electronic devices are supported by multicore processors and they have become an unavoidable part of recent technologies. The Arithmetic Logic Unit (ALU) is one of the indispensable parts of the Central Processing Unit (CPU) which performs most of the operations. Operations like multiplications, and exponentials consume more power than other normal operations. Power management is one of the major challenges in designing processors. To maximize speed and reduce power consumption, a new technique in Multiplier and ALU incorporated with a multicore processor has been proposed. The Proposed Approximate Compatible ALU (ACALU) is designed to perform specified operations that consume more power, using an advanced multiplication technique called the First One First Operand (FOFO) method. The selection process of eight bits is done by the FOFO method followed by error detection and error approximation is performed to get the accurate output. The ACALU performs these operations in the Approximate Computing Mode which utilizes only eight bits for the operations, thus reducing the power consumption. The results of several analyses between multipliers, ALUs, and microprocessors are provided. As we optimize the multiplier and ALU unit, the multicore processor is also enhanced. The proposed multicore processor is compared with the AMD processor and the latest INTEL processor and the comparison results show that the proposed technique is 95.2% and 97.8% more efficient than the existing processors. Thus, the power consumption is minimized and the performance speed is increased in the proposed multicore processor.

We obtain all Dirichlet spaces ℱ_q, q ∈ ℝ, of holomorphic functions on the unit ball of ℂ^N as weighted symmetric Fock spaces over ℂ^N. We develop the basics of operator theory on these spaces related to shift operators. We do a complete analysis of the effect of q ∈ ℝ in the topics we touch upon. Our approach is concrete and explicit. We use more function theory and reduce many proofs to checking results on diagonal operators on the ℱ_q. We pick out the analytic Hilbert modules from among the ℱ_q. We obtain von Neumann inequalities for row contractions on a Hilbert space with respect to each ℱ_q. We determine the commutants and investigate the almost normality of the shift operators. We prove that the C*-algebras generated by the shift operators on the ℱ_q fit in exact sequences that are in the same Ext class. We identify the groups K₀ and K₁ of the Toeplitz algebras on the ℱ_q arising in K-theory. Radial differential operators are prominent throughout. Some of our results, especially those pertaining to lower negative values of q, are new even for N = 1. Many of our results are valid in the more general weighted symmetric Fock spaces ℱ_b that depend on a weight sequence b.

We propose that genetic encoding of self-assembling components greatly enhances the evolution of complex systems and provides an efficient platform for inductive generalization, i.e. the inductive derivation of a solution to a problem with a potentially infinite number of instances from a limited set of test examples. We exemplify this in simulations by evolving scalable circuitry for several problems. One of them, digital multiplication, has been intensively studied in recent years, where hitherto the evolutionary design of only specific small multipliers was achieved. The fact that this and other problems can be solved in full generality employing self-assembly sheds light on the evolutionary role of self-assembly in biology and is of relevance for the design of complex systems in nano- and bionanotechnology.

A method that constructs an MRA E-tight frame wavelet by using a generalized low pass E-filter is given, and it is showed that all of MRA E-tight frame wavelets can be obtained via the method, where the dilation matrix E is the quincunx matrix or the matrix consists of (0, 1)^T and (2, 0)^T. Furthermore, the properties of MRA E-tight frame wavelet multipliers as well as E-pseudoscaling function multipliers and generalized low pass E-filter multipliers are characterized. In addition, as an application of these multipliers, we discuss the connectivity of the set of all MRA E-tight frame wavelets in L²(R²).

In this paper, we study the space of 3-Lie multipliers on Banach 3-Lie algebras. Moreover, we investigate a characterization of 3-Lie multipliers on commutative and without order Banach 3-Lie algebras. Finally, we establish the stability and superstability of 3-Lie multipliers.

The random Dirichlet type functions on the unit ball of Cⁿ are studied. Sufficient conditions of the multipliers of for 0 < μ ≤ 1, if n = 1 or 0 < μ < 2 if n > 1 are given. The smoothness of random Dirichlet type functions is discussed.

Let $L$ be a non-abelian nilpotent Lie algebra of dimension $n$ and put $s(L)=\frac{1}{2}(n-1)(n-2)+1-\mathrm{\text{dim}}{ℳ}(L)$, where ${ℳ}(L)$ denotes the Schur multiplier of $L$. Niroomand and Russo in 2011 proved that $s(L)\ge 0$ and that $s(L)=0$ if and only if $L\cong H(1)\oplus F(n-3)$, in which $H(1)$ is the Heisenberg algebra of dimension $3$ and $F(n-3)$ is the abelian $(n-3)$-dimensional Lie algebra. In the same year, they also classified all nilpotent Lie algebras $L$ satisfying $s(L)=1$ or $2$. In this paper, we obtain all nilpotent Lie algebras $L$ provided that $s(L)=3$.