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In this paper, four instrumentation amplifier (IA) topologies, one of which is current-mode (CM) while the others are voltage-mode (VM), are presented. Three of the IAs use one to two current feedback operational amplifiers (CFOAs) while the other one employs only a single NMOS transistor. One of the IA circuits, given as an example, is simple while others are novel. The CM IA is composed of only grounded resistors which have some advantages in integrated circuit (IC) process. Non-ideality effects such as non-ideal gain and parasitic impedances on the performance of introduced IAs are discussed. In order to show the performance of the circuits, we perform experimental tests and simulations by using SPICE program.

In this paper, a new current-mode (CM) circuit for realizing all of the first-order filter responses is suggested. The proposed configuration contains low number of components, only two NMOS transistors both operating in saturation region, two capacitors and two resistors. Major advantages of the presented circuit are low voltage, low noise and high linearity. The proposed filter circuit can simultaneously provide both inverting and non-inverting first-order low-pass, high-pass and all-pass filter responses. Computer simulation results achieved through SPICE tool and experimental results are given as examples to demonstrate performance and effectiveness of the proposed topology.

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.