Narrow Results

In order to see the effect of interfacial layer on electrical characteristics both Au/n–4H–SiC (MS) and Au/TiO₂/n–4H–SiC (MIS) type Schottky barrier diodes (SBDs) were fabricated and their main electrical parameters were investigated by using the forward and reverse bias current-voltage (I–V), capacitance/conductance-voltage (C/G–V) measurements at room temperature. The ideality factor (n), series and shunt resistances (R_s, R_sh), barrier height (BH), depletion layer width (W_D) and the concentration of donor atoms (N_D) were obtained before and after illumination. The energy density distribution profile of surface states (N_ss) was also obtained by taking into account voltage dependent effective BH (Φ_e) and ideality factor (n_V). All of these experimental results confirmed that the use of a high dielectric material or insulator layer (TiO₂) between metal and semiconductor leads to improvements in the diode performance in terms of R_s, R_sh, BH, N_ss and rectifier rate (RR = I_F/I_R for sufficiently high forward and reverse current). Another important result is the negative capacitance (NC) behavior observed in the forward bias C–V plot for the Au/n–4H– SiC (MS) diode, but it disappears in Au/TiO₂/n–4 H–SiC (MIS) diode and also the minimum value of C–V plot corresponds to maximum value of G/ω–V plot in the accumulation region. Such behavior of NC shows that the material displays an inductive behavior.

In this paper, we investigate the impact of random dopant fluctuation (RDF) on the statistical variations in negative capacitance MOSFETs (NCFETs) through a device simulation coupled with the Landau–Khalatnikov (LK) equation. Compact models for feedback mechanisms that are based on the internal gate voltage amplification in NCFETs are proposed. The results show that internal voltage amplification plays a decisive role in performance improvement of device variability. Further, our simulation study demonstrates that owing to the feedback mechanism, the dispersions of the performance parameters in NCFETs exhibit different statistical distribution characteristics compared to their MOSFET counterparts. Our study may provide further insight regarding device and/or circuit designs utilizing NCFETs.

In this paper, a negative capacitance (NC) effect in series with normal oxide capacitance is first time introduced to design negative capacitance charge plasma-based junction less vertical TFET structure (NC-CP-JL-VTFET). The introduced negative capacitance enhances the overall gate capacitance and hence gate capacitive coupling and thus renders high current capabilities with reduced sub-threshold slope and threshold voltage. With the use of negative capacitance along with oxide capacitance, it has been seen that the same drain current is achieved at lower gate voltage as compared to without use of negative capacitance and since the voltage scaling is done considerably, the dynamic power dissipation in circuit application can be reduced significantly. To generate the negative capacitance during the device operation; ferroelectric material $P$(VDF-TrFE) poly(vinylidene fluoride-trifluoro ethylene) is used in stack with SiO₂ gate oxide. Various performance parameters of the designed structure such as electron–hole concentration in the tunneling junction, electric field, surface potential, electron–hole quasi-Fermi variation, and drain current variation are investigated and compared with the results of without considering the ferroelectric material in the gate oxide. The variation of the ferroelectric thickness on the device performance is also investigated. The investigation exhibits significant improvement in the drain current and in the other parameters as well. These improvements are seen because of higher capacitive coupling and these effects are further responsible for more energy band bending which in turn govern high electron tunneling. Due to the existence of negative capacitance, the peak value of the electric field gets doubled while the surface potential increases 44% from the normal structure.

Differential capacitance is derived based upon energy, charge or current considerations, and determined when it may go negative or positive. These alternative views of differential capacitances are analyzed, and the relationships between them are shown. Because of recent interest in obtaining negative capacitance for reducing the subthreshold voltage swing in field effect type of devices, using ferroelectric materials characterized by permittivity, these concepts are now of paramount interest to the research community. For completeness, differential capacitance is related to the static capacitance, and conditions when the differential capacitance may go negative in relation to the static capacitance are shown.

Progress in electronics is limited by power dissipation constraints. Ferroelectric materials with a negative capacitance could help to overcome these limits. Especially, HfO₂ and ZrO₂ based ferroelectrics are promising for negative capacitance electronics due to their compatibility with modern transistor manufacturing processes. Recently, first negative capacitance transistors have been demonstrated. However, further investigations on the microscopic origin of negative capacitance in HfO₂- and ZrO₂-based ferroelectrics are needed. Lastly, opportunities for negative capacitance beyond transistors are discussed.