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Multidimensional torus networking topology has become widespread recently in the domain of high-performance computers, clusters, and grids, as well as in the domain of networks on chip. Torus represents an ideal communication structure with the shortest distance and multitude of alternative shortest paths between a pair of nodes. We study simple and powerful local packet forwarding (switching) rules that provide packet delivery with quasi-optimal load balancing and do not use tables of addresses (routes). Implementation of these rules in the form of micro-program code within switching nodes increases considerably network performance, security, and QoS. We use infinite Petri nets and reenterable models in the form of colored Petri nets for prototyping the multi-dimensional torus interconnect simulator to study and compare the packet forwarding rules. Then, an ad-hoc simulator of torus interconnect ts is implemented in the C language to provide high performance and the possibility of simulation over prolonged intervals of time. The simulation results acknowledge the advantages of local packet forwarding rules.

A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and torus networks. In addition, we propose the network-on-chip (NoC) implementation of MMN. With innovative combination of diagonal and hierarchical structure, the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. The simple architecture of MMN is also highly suitable for NoC implementation. To implement all the links of level-3 MMN, only four layers are needed which is feasible with current and future VLSI technologies.

Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs). In an SoC, the placement of the communicating elements across the network has an impact on system performance. Such a placing is called the MAPPING phase in networks on chip design process. Many approaches dealing with the mapping phase have been proposed but selecting the best technique for a given NoC remains a challenging problem. This paper attempts to provide an answer to this issue. It motivates and presents a definition and a classification according to some criteria: (i) the algorithms used for solving the mapping problem, (ii) the moment in which the mapping is executed, (iii) the impact of combining mapping with other phases during NoC design and (iv) the target architecture.

This paper investigates the techniques to construct high-quality target processor array (fault-free logical subarray) from a physical array with faulty processing elements (PEs), where a fixed number of spare PEs are pre-integrated that can be used to replace the faulty ones when necessary. A reconfiguration algorithm is successfully developed based on our proposed novel shifting operations that can efficiently select proper spare PEs to replace the faulty ones. Then, the initial target array is further refined by a carefully designed tabu search algorithm. We also consider the problem of constructing a fault-free subarray with given size, instead of the original size, which is often required in energy-efficient MPSoC design. We propose two efficient heuristic algorithms to construct target arrays of given sizes leveraging a sliding window on the physical array. Simulation results show that the improvements of the proposed algorithms over the state of the art are $19\%$ and $16\%$, in terms of congestion factor and distance factor, respectively, for the case that all faulty PEs can be replaced using the spare ones. For the case of finding $64\times 64$ target array on $128\times 128$ host array, the proposed heuristic algorithm saves the running time up to $99\%$ while the solution quality keeps nearly unchanged, in comparison with the baseline algorithms.

The wireless network on chip WiNoC introduces wireless links in the traditional network on chip (NoC), which reduces the network diameter and enables high-throughput, low-latency data communications. In addition, if wireless nodes can dynamically request data transmission, wireless bandwidth will be more effectively utilized. In order to implement a conflict-free, adaptive bandwidth allocation strategy, a priority-based dynamic media access control mechanism has been designed. In this work, a dynamic priority calculation method has been proposed based on the packets’ transmission time and the waiting time in the queue. Then, a priority calculating unit is designed to calculate the dynamic priority of the packet. Finally, the central control unit designed obtains the dynamic priority of the packets, and dynamically authorizes the use rights of the wireless medium according to the priority of the data packet. Simulation experiments show that the media access control mechanism proposed in this paper has significant improvements in throughput, delay, and power consumption performances compared with other mechanisms [S.Deb et al., Wireless NoC as interconnection backbone for multicore chips: promises and challenges, IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (2012) 228–239].

Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the $6\times 6$ mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the $6\times 6$ mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively.