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C-based cycle-accurate simulations are used to evaluate the performance of a Network-on-Chip (NoC) based on an improved version of the modified Fat Tree topology. The modification simplifies routing further and guarantee orderly reception of packets without any loss of performance. Several traffic models have been used in these simulations; Bursty and non-bursty traffic with uniformly-distributed destination addresses and non-uniformly-distributed destination addresses. A simple new traffic model has been developed for generating non-uniformly-distributed destination addresses. This model is general enough to be used in developing new NoC architectures and captures universally accepted place-and-route methodologies. Simulation results are used to illustrate how the hardware resources of a modified Fat Tree NoC can be minimized without affecting the network performance. The performance of a NoC with regular Mesh topology was also evaluated for comparison with the modified Fat Tree topology.

As networks-on-chips (NoCs) are expected to provide the necessary scalable communication medium for future many-core systems-on-chips (SoCs) optimizing their resources is of great importance. What is really needed is an efficient NoC architecture with optimized resources that requires very little customization by the SoC developers. One of the most important area and power hungry resources is the NoC's buffers. In this work, a new Modified Fat Tree (MFT) NoC architecture with buffers engineered for maximum efficiency (performance versus area) is presented. Extensive simulations are used to show optimum buffer design/placement under different conditions of traffic types and NoC sizes.

This paper presents a hierarchical fault-tolerant routing algorithm called FXY, which is a hybrid method based on flooding and XY, and can balance performance and fault tolerance based on a predefined parameter m. First, FXY partitions the whole network into different equal size square submeshes with the size of m × m. At the first level of the hierarchy, packet routing within these submeshes is performed based on flooding routing algorithm. When the packets are received at effective boundary of each submesh, XY routing is performed to route the packet inter submeshes i.e., from one submesh to the neighbor submesh which is certainly one of its neighbor nodes. Here, the size of the submesh is defined as fault-tolerant granularity. As fault-tolerant granularity is increased, the size of the submeshes will be increased, therefore the method mainly floods packets in large-size submeshes and finally packets are received at their destinations correctly. On the other hand, when fault-tolerant granularity is decreased, the method mainly routes packets as XY method, which is not fault-tolerant, but has the best performance. The method is evaluated for various packet injection rates and fault rates. The experimental results reveal that the method presents a fault-tolerant routing algorithm, and can be adjusted so that it shows better fault-tolerance and performance trade-offs compared to XY and flooding which are two end-to-end cases of having the best performance and no fault-tolerance, having the least performance and the best fault tolerance, respectively. The experimental results for an 8 × 8 NoC size, have shown that 2-FXY, which is the proposed method with fault-tolerant granularity of two, offers the best trade-off between performance and fault tolerance compared to other methods, XY, flooding and probabilistic flooding.

Reliability is one of the main concerns in the design of networks-on-chip (NoCs) due to the use of deep submicron technologies in fabrication of such products. This paper presents a new fault-tolerant routing algorithm called double stairs for NoCs. Double stairs routing algorithm is a low overhead routing that has the ability to deal with fault. The proposed routing algorithm makes a redundant copy of each packet at the source node and routes the original and redundant packets in a new partially adaptive routing algorithm. The method is evaluated for various packet injection rates and fault rates. Experimental results show that the proposed routing algorithm offers the best trade-off between performance and fault tolerance compared to other routing algorithms, namely flooding, XYX and probabilistic flooding.

In a resource-constrained environment of the 21st century, the use of hardware-based reconfigurable systems such as Field Programmable Gate Array (FPGAs) is considered an effective way to enhance information security. In comparison with traditional custom circuitry that does not give a flexible approach, it is observed that the reconfigurable hardware shows an excellent potential for cyber security by increasing hardware speeds and flexibility. Therefore, in a quest to integrate multi-core systems, the Network-on-Chip (NoC) has become one of the popular widespread techniques to maximize router security. Due to the significant overhead of chip space and the power consumption of the routers, it is substantially more expensive to construct as compared to a bus-based system. The control component (CC) interacts with the networks that inject packets based on router switching and activity. These control components are coupled with each network to produce a system of controlled networks. The system is further linked with CFM or a Centralized Fabric Manager, which serves as the network’s focal point. After that, the CFM runs the algorithm regularly. The analytic parameters comprise flip flop, power, latency, number of lookup tables (LUTs), and throughput. In the proposed method, the number of LUTs is $0.35{\mathrm{\text{mm}}}^2$, the flip flop is $3.5{\mathrm{\text{mm}}}^2$, the power is $3.4\mu$W, the latency is 5941ns, and the planned throughput is 0.56 flits/cycle. Results indicate that the crossbar switch reduces errors and minimizes the delay in the architecture’s outcome level, which further overcomes the descriptions of performance, power throughput, and area delay parameters. The findings of the research can be useful to enhance information security among lightweight devices besides minimizing the chances of network attacks in today’s dynamic and complex cyberspace.