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The von Neumann bottleneck in traditional computers has hindered the rapid development of artificial intelligence. To improve computational efficiency, memristors have become a preferred device to mimic synaptic behavior and achieve neuromorphic computing, thus attracting widespread attention. In this work, La:HfO₂/ZrO₂/La:HfO₂ thin films were prepared via sol–gel deposition. When Zr was inserted as an interlayer into 6% La-doped HfO₂, the significant resistance switching (RS) behavior was detected through voltage scanning over 100 consecutive cycles, and its electrical performance was enhanced compared to the case when there was no interlayer. The presence of an Analog resistance switch enabled the device to effectively simulate synaptic properties such as the long-term potentiation/inhibition, short-term potentiation/inhibition, paired-pulse facilitation, and spike-timing-dependent plasticity learning rules. Moreover, the device exhibited good linearity in weight updates and excellent conductance modulation performance. Utilizing a convolutional neural network architecture, information in a $28\times 28$ pixel array was classified and processed, thereby improving the recognition accuracy of Mixed National Institute of Standards & Technology (MNIST) dataset to 97.5% and that of Fashion-MNIST dataset to 87.0%. These advancements have provided a viable solution for the successful construction of artificial neural network systems in the future.

This study investigates the use of neuromorphic computing, particularly spiking neural networks (SNNs) and advanced neuromorphic hardware, to model and forecast climate patterns. Our neuromorphic system achieves high prediction accuracy, maintaining a Mean Squared Error (MSE) as low as 0.08, even with increasing data volumes. The system operates with notable energy efficiency, consuming just 0.15 J per inference at higher data loads. This efficiency, coupled with a throughput of 800 inferences per second, underscores the system’s capability to handle large-scale data effectively. The neuromorphic approach addresses key challenges in scalability and energy consumption, presenting a robust solution for real-time climate data analysis. By continuously adapting to new data inputs, the system ensures accurate and timely predictions, essential for applications in environmental monitoring and decision-making. The integration of artificial intelligence algorithms with neuromorphic architectures not only reduces computational costs but also enhances the interpretability of complex climate dynamics. These findings highlight the transformative potential of brain-like computing in environmental modeling, offering a scalable, efficient, and adaptable tool for climate prediction and analysis.

Contrary to von Neumann computer architecture, neuromorphic computing is a biologically inspired method for building several sorts of brain-inspired computers. This computer technology uses silicon neurons and synapses to solve difficult machine learning and AI challenges. The goal of neuromorphic computing is to build a brain-like ability to compute, learn, and adapt. Building an appropriate neuroscience model, establishing a new architecture, modeling new devices, finding new materials for the devices, programming framework, and applications for these neuromorphic devices are major technological challenges. This study covers numerous neuron models from Hodgkin–Huxley to I&F, mathematical equations, circuit level analysis and motivations for neuromorphic computing. Here some of the most useful silicon neuron models are discussed in terms of biological plausibility, computational efficiency, and temperature dependency. This survey shows that more than 52 transistors make up the silicon HH neuron, which occupies less than 0.01${\mathrm{\text{mm}}}^2$ and consumes 60uW of power. On the other hand, an I&F neuron needs less than 20 transistors, occupies 442${\mathrm{\text{um}}}^2$ and consumes 40pW of power.

Neuromorphic systems are the future computing systems to overcome the von Neumann’s power consumption and latency wall between memory and processing units. The two main components of any neuromorphic computing system are neurons and synapses. Synapses carry the weight of the system to be multiplied by the neuromorphic attributes, which represent the features of the task to be solved. Memristor (memoryresistor) is the most suitable circuit element to act as a synapse. Its ability to store, update and do matrix multiplication in nanoscale die area makes it very useful in neuromorphic synapses. One of the most popular memristor synapse configurations is the two-transistor–one-memristor (2T1M) synapse. This configuration is very useful in neuromorphic synapses for its ability to control reading and updating the weight on a chip by signals. The main problem with this synapse is that the reading operation is destructive, which results in changing the stored weight value. In this paper, a novel refreshment circuit is proposed to restore the correct weight in case of any destructive reading operations. The circuit makes a small interrupt time during operation without disconnecting the memristor, which makes the circuit very practical. The circuit has been simulated by using hardware-calibrated CMOS TSMC 130nm technology on Cadence Virtuoso and linear ion drift memristor Verilog-A model. The proposed circuit achieves the refreshment task accurately for several error types. It is used to refresh 2T1M synapse with any destructive reading signal shape.

Memcapacitors (MCs) are promising candidates for the future design of low-power integrated neuromorphic computing systems, with particular emphasis on dynamical spiking neuron models that exhibit rich temporal behaviors. We present a novel floating flux-controlled MC that is designed using only three current feedback amplifiers, one analog multiplier, one capacitor and one resistor. Compared with existing floating MC emulators, our proposed design has a simpler structure without the need for DC biasing voltage sources, and can operate at higher working frequencies, and therefore enabling rapid prototyping of applied MC circuits for experimental verification of large-scale MC arrays. The consistency of the theoretical analysis, simulation and experimental results confirms the correctness and practicability of this new memcapacitor emulator. To further demonstrate a potential use of our MC, in this work, we apply the MC as the first parameterizable leaky integrator for spiking neuron through simulation and experiments. The intrinsic tunable capacitance of the MC can bring about novel short-term memory dynamics to neuronal circuits by dynamically modifying the membrane time constant on-the-fly, which ultimately resembles long-term potentiation, and can thus offer longer term memory.

Our results highlight the potential for integrating heterogeneous spiking neural networks with richer temporal dynamics that rely on MC-based circuits to further the capability of neuromorphic computing.

A system of drift-diffusion equations for the electron, hole, and oxygen vacancy densities in a semiconductor, coupled to the Poisson equation for the electric potential, is analyzed in a bounded domain with mixed Dirichlet–Neumann boundary conditions. This system describes the dynamics of charge carriers in a memristor device. Memristors can be seen as nonlinear resistors with memory, mimicking the conductance response of biological synapses. In the fast-relaxation limit, the system reduces to a drift-diffusion system for the oxygen vacancy density and electric potential, which is often used in neuromorphic applications. The following results are proved: the global existence of weak solutions to the full system in any space dimension; the uniform-in-time boundedness of the solutions to the full system and the fast-relaxation limit in two space dimensions; the global existence and weak–strong uniqueness analysis of the reduced system. Numerical experiments in one space dimension illustrate the behavior of the solutions and reproduce hysteresis effects in the current–voltage characteristics.

The paper attempts to bridge the gap between widely accepted models of biological systems based on the Tsetlin automata acting in random environment and traditional artificial neural networks that consist of the McCalloch and Pitts neurons. Using recently developed algebra with uninorm and absorbing norm aggregators, we consider the neurons as extended Tsetlin automata that implement multi-valued not - xor operator applied to the aggregated inputs and internal states, and then construct the network using these neurons. The inputs of the neurons are specified by the synapses that implement multi-valued joined and and or operations. We demonstrate that for favorable (in the sense of learning) states the suggested neurons act similarly to the traditional neurons, while for unfavorable states they immediately change their activity to the reverse one. Such properties of the neurons both results in the correct activity of the network and demonstrates better correspondence with the logics of natural neural networks.

The next generation of artificial intelligence systems is generally governed by a new electronic element called memristor. Memristor-based computational system is responsible for confronting memory wall issues in conventional system architecture in the big data era. Complementary Metal Oxide Semiconductor (CMOS) compatibility, nonvolatility and scalability are the important properties of memristor for designing such computing architecture. However, some of the concerns, such as analogue switching and stochasticity, need to be addressed for the use of memristor in novel architecture. Here, we reviewed a number of important scientific works on memristor materials, electrical performance and their integration. In addition, strategies to address the challenges of memristor integration in neuromorphic computing are also being investigated.

Over the last decade, artificial intelligence (AI) has found many applications areas in the society. As AI solutions have become more sophistication and the use cases grew, they highlighted the need to address performance and energy efficiency challenges faced during the implementation process. To address these challenges, there has been growing interest in neuromorphic chips. Neuromorphic computing relies on non von Neumann architectures as well as novel devices, circuits and manufacturing technologies to mimic the human brain. Among such technologies, three-dimensional (3D) integration is an important enabler for AI hardware and the continuation of the scaling laws. In this paper, we overview the unique opportunities 3D integration provides in neuromorphic chip design, discuss the emerging opportunities in next generation neuromorphic architectures and review the obstacles. Neuromorphic architectures, which relied on the brain for inspiration and emulation purposes, face grand challenges due to the limited understanding of the functionality and the architecture of the human brain. Yet, high-levels of investments are dedicated to develop neuromorphic chips. We argue that 3D integration not only provides strategic advantages to the cost-effective and flexible design of neuromorphic chips, it may provide design flexibility in incorporating advanced capabilities to further benefit the designs in the future.

Due to their nonvolatility and intrinsic current integration capabilities, spintronic devices that rely on domain wall (DW) motion through a free ferromagnetic track have garnered significant interest in the field of neuromorphic computing. Although a number of such devices have already been proposed, they require the use of external circuitry to implement several important neuronal behaviors. As such, they are likely to result in either a decrease in energy efficiency, an increase in fabrication complexity, or even both. To resolve this issue, we have proposed three individual neurons that are capable of performing these functionalities without the use of any external circuitry. To implement leaking, the first neuron uses a dipolar coupling field, the second uses an anisotropy gradient and the third uses shape variations of the DW track.