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Low noise amplifier (LNA) is an important component in RF receiver front end. An inductively degenerated cascode low noise amplifier (IDCLNA) is mostly preferred for producing good trade-offs such as high gain, low noise figure (NF), high reverse isolation and low power consumption for narrowband applications. This IDCLNA structure is also used to reduce the gate induced noise on the noise performance by inserting the capacitance in parallel with the gate-to-source capacitance of main transistor. Usually, the parasitic overlap capacitances can impose serious constraints on achievable performance and is taken into account in IDCLNA. In this paper, IDCLNA is designed at a frequency of 2.4 GHz with analyzing the impact of parasitic overlap capacitances on IDCLNA in terms of unity current gain frequency (f_T) which will affect the NF of IDCLNA and simulated using 130 nm, 90 nm and 65 nm CMOS technologies. The NF of IDCLNA with and without parasitic overlap capacitances are analyzed and compared for different short channel CMOS processes. Simulation results show that the parasitic overlap capacitances have advantageous to reduce the gate induced noise in IDCLNA for 130-nm CMOS process for 2.4 GHz applications.

To obtain certain information such as metabolic concentrations in neural or muscular tissues and other applications, it is necessary to design nuclear magnetic resonance (NMR) transmitters/receivers capable of operating at multiple frequencies, while maintaining a good performance at each frequencies. We have proposed a new NMR receiver front-end for simultaneous detection of proton and carbon nucleus. The system consists of two reception coils for carbon and hydrogen analysis, a multiband low-noise amplifier (LNA) for increasing the voltage level and a network for passive amplification, noise figure minimization and decreasing mutuality effect between two coils. The proposed coil set was designed, simulated and analyzed and also the signal to noise ratio (SNR) with quality factor have been calculated for it by simulation. The LNA has been designed in a 0.18$\mu$m CMOS technology and its gains for carbon and proton NMR signals are 45 and 48dB, respectively. The input referred noise for both signals is lower than 0.4nV/sqrt(Hz) and the power consumption is 4 mA from a single 1.8V supply.

In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18$\mu$m CMOS process. The designed LNA shows a gain of 15.28dB, NF of 0.376dB, the power dissipation of 936$\mu$W and IIP3 of $-4.36$dBm at 2.4GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3mW${}^{-1}$ and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.

This paper presents an inductor less wideband low noise amplifier (LNA) with an area of 0.3mm², using 130nm SiGe BiCMOS technology targeted for 5G WiGig wireless application. A $g_m$ boosting amplifier used at the intermediate node of the cascode topology to reduce the noise contribution of the common base (CB) transistor for the first time in SiGe HBT technology. Mathematical analysis shows that the proposed high frequency $g_m$ boosting technique on the CB transistor can be optimally tuned for either low NF or high linearity. Furthermore, the circuit incorporates variable capacitors for multimode capability, ensuring optimal performance in all four WiGig channels. Post layout EM simulation of the circuit shows that the resultant LNA has a maximum gain of 21.08dB with the $-$3 dB frequency over 56GHz to 67.3GHz. The proposed LNA exhibits a minimum noise figure of 4.3dB and shows high linearity with an input referred $IP3$ of $-$2.7dB. The designed when operated using supply voltage of 1.2V consumes a total dc power of 8.9mW.

An oscillator is a vital component as the energy source in microwave telecommunication system. Microwave oscillators designed using Gunn diode have poor DC to RF efficiency. IMPact Ionization Avalanche Transit-Time diode (IMPATT) oscillators have the drawback of poor noise performance. The transistorized oscillators have a limitation to the maximum oscillation frequency which means that they cannot be used for oscillators designed for high frequencies. To design negative series feedback Dielectric Resonator Oscillator (DRO), the resonant unit uses a dielectric resonator (DR) since it is small in size, light in weight, has high-Quality ($Q$) factor, better stability and also it is inexpensive. It has the benefits of low-phase noise, low cost, miniaturization, high stability, applicable for devices designed at high frequencies and had already been widely applied, so the research on microwave dielectric oscillator has also been one of the focus of today’s microwave integrated circuits. DRO is widely used in electronic warfare, missile, radar and communication systems. The DRO incorporates High-Electron Mobility Transistor (HEMT) as an active device since it offers higher power-added efficiency combined with excellent low-noise figures and performance. The entire circuit of DRO using HEMT at 26GHz is designed using Agilent Advanced Design System (ADS) software. In this, DRO different measurements of parameters are done such as output power which is typically $+11$dBm for 26GHz DRO, phase noise at 10kHz offset for 26GHz DRO it is 80dBc/Hz. The frequency pushing and frequency pulling for 26GHz DRO its typical values are 30kHz/V and 1MHz, respectively.

This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18-$\mu$m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5GHz, while less than 0.78mW is consumed from a 1.5-V supply. A noise figure of 23.7dB is measured. Also, the VGA achieves a gain control range of 19dB with a gain error less than $\pm 0.5$dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications.