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An intelligent integrated environment that provides decision support for printed circuit board (PCB) assembly is presented. This simulation-based decision support system enables manufacturing engineers, with little or no simulation experience, to exploit this technology fully for design and management of PCB assembly lines. PCB lines are selected for their simplicity in representation but stochasticity in nature of product demand and change. Within the environment is the capability to design graphically simulation models mapped to the real system, to define desired production targets, to execute a base language model and to generate results that can be intelligently analysed and presented for remedial action. A case example is also presented.

This paper proposes a sequencing approach to develop a competent path for the printed circuit board assembly process. An efficient heuristic is developed that determines the component placement sequence, also referred to as the placement path. This NP-complete problem best resembles a Traveling Salesman Problem.¹ Thus, it is inherently difficult. The heuristic approach is tested against a previously published subproblem as well as a real-life working board configuration. This heuristic is intended to provide a good, feasible component placement sequence for the assembly of a batch of printed circuit boards with a machine configuration consisting of a moveable X-Y positioning table and a tape-and-reel sliding feeder rack. Even with high speed assembly machines placing in excess of 40000 components per hour (cph), process improvements are possible by increasing the efficiency of the planned placement sequence. This heuristic is developed to identify an improved component placement sequence in a reasonable computation time to allow for future implementation of the methodology in applied situations where time constraints are unavoidable.

Electroplating is a major process in the manufacturing of printed circuit boards. Scheduling the movement of material handling hoists for electroplating processes is generally known as the Hoist Scheduling Problem (HSP) and has been proven to be NP-complete. The objective of HSP is to find a cyclic sequence of hoist moves that maximizes the production throughput. For the past two decades, various optimization and heuristic techniques have been proposed to solve the problem. However, these methods are often limited to the elementary problems. Recently, artificial intelligence (AI) approach using constraint logic programming has been applied to solve the cyclic HSP, but did not consider problems with duplicated process tanks. In this paper, we apply constraint satisfaction to solve HSP with duplicate process tanks. A binary search procedure is proposed and a tighter bound to the cycle length is introduced to reduce the computation effort. The proposed algorithm can be easily implemented on any personal computer with reasonable performance so as to be useful on the shop floor. Finally, we present results for several benchmark examples.

This paper summarizes a study of chip scale packages (CSP) to determine their maximum allowable power dissipation within typical system level environments. These results can be used to determine the applicability of utilizing CSPs from the standpoint of die power dissipation. Both steady state and transient thermal performance is covered in this study. The steady state portion used in-house software, while closed-form solutions were utilized for the transient analysis. The steady state power limit, while governed by a number of parameters, is dependent mainly upon system level parameters (heatsinking, cooling mode — i.e., natural or forced convection, and PCB power loading). Thermal enhancement features (e.g. thermal vias and bumps) are not generally effective in increasing the maximum power that can be dissipated by the package in the end use environment. The variables investigated in the steady state study included die size, thermal vias and bumps, the addition of a heatsink, natural/forced convection boundary conditions, printed circuit board (PCB) heat loading, and PCB thermal conductivity. The transient portion considered die size, pulse shape and duration, and the addition of a heatsink. For relatively short duration transients (e.g. switching an inductive load), the power limit is governed by the die geometry; magnitude, shape and duration of the heating pulse; and the starting and maximum allowable temperatures of the junction.