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This paper discusses commonly used reverse engineering methods to illegally recreate printed circuit board (PCB) designs. A solution using transformative electronics is presented to prevent the discussed reverse engineering methods by obfuscating the design. The transformative electronics solution is employed in a specific application that results in a reverse engineered board to be incorrectly recreated, where the signals would be distorted due to added electromagnetic interference (EMI). The non-conductive vias that are part of the obfuscation would allow the inclusion of EMI generators that would not affect the circuit in an original design but would prevent copied designs from working correctly. A machine learning algorithm is being designed to optimize the placement of the EMI sources in an original PCB.

To prevent any negative electromagnetic influence of high-density integrated circuits, an insulation package needs to be specially designed to shield it. Aiming at the low efficiency and material waste in traditional packaging methods, a printed circuit board (PCB) selective packaging system based on a multi-pattern solder joint simultaneous segmentation algorithm and three-dimensional printing technology is introduced in this paper. Firstly, the structure of PCB selective packaging system is designed. Secondly, to solve the existing problems, such as multi-pattern solder joints which are located densely in small welding areas and are hard to be extracted in the small-area integrated circuit board, a multi-pattern solder joint simultaneous segmentation algorithm is developed based on (geometrical) neighborhood features to extract and locate the optimal PCB solder joint areas. Finally, tests using three actual PCB are carried out to compare the proposed method with traditional multi-threshold solder joint extraction methods. Test results indicate that the proposed algorithm is simple and effective. Diverse solder joints can be optimally located and simultaneously extracted from the collected PCB image, which greatly improves the filling rate of the solder joint areas and filters out false pixels. Thus, this method provides a reliable location-finding tool to help place solder points in PCB selective packaging systems.

Advances in magnetoresistive type sensors provide a new technique for nondestructive evaluation of metal structures. Giant magnetoresistive and giant magnetoimpedance sensors provide high sensitivity and reduced size with GMI sensors also adding capabilities of high frequency range of measurements. Being produced with thin film processing techniques, the manufacturing cost of these sensors is low. An example is considered of detecting defects in printed circuit boards. System details and experimental results are provided. Computational modeling validation is introduced based on finite element as well as method of moments analysis.

The demand for better tools for machining printed circuit boards (PCBs) is increasing due to the extensive usage of these boards in digital electronic products. This paper is aimed at optimizing coating type on micro drills in order to extend their lifetime in PCB machining. First, the tribotests involving micro crystalline diamond (MCD), nano crystalline diamond (NCD) and bare tungsten carbide (WC-Co) against PCBs show that NCD–PCB tribopair exhibits the lowest friction coefficient (0.35) due to the unique nano structure and low surface roughness of NCD films. Thereafter, the dry machining performance of the MCD- and NCD-coated micro drills on PCBs is systematically studied, using diamond-like coating (DLC) and TiAlN-coated micro drills as comparison. The experiments show that the working lives of these micro drills can be ranked as: NCD$>$TiAlN$>$DLC$>$MCD$>$bare WC-Co. The superior cutting performance of NCD-coated micro drills in terms of the lowest flank wear growth rate, no tool degradation (e.g. chipping, tool tipping) appearance, the best hole quality as well as the lowest feed force may come from the excellent wear resistance, lower friction coefficient against PCB as well as the high adhesive strength on the underneath substrate of NCD films.

An intelligent integrated environment that provides decision support for printed circuit board (PCB) assembly is presented. This simulation-based decision support system enables manufacturing engineers, with little or no simulation experience, to exploit this technology fully for design and management of PCB assembly lines. PCB lines are selected for their simplicity in representation but stochasticity in nature of product demand and change. Within the environment is the capability to design graphically simulation models mapped to the real system, to define desired production targets, to execute a base language model and to generate results that can be intelligently analysed and presented for remedial action. A case example is also presented.

This paper proposes a sequencing approach to develop a competent path for the printed circuit board assembly process. An efficient heuristic is developed that determines the component placement sequence, also referred to as the placement path. This NP-complete problem best resembles a Traveling Salesman Problem.¹ Thus, it is inherently difficult. The heuristic approach is tested against a previously published subproblem as well as a real-life working board configuration. This heuristic is intended to provide a good, feasible component placement sequence for the assembly of a batch of printed circuit boards with a machine configuration consisting of a moveable X-Y positioning table and a tape-and-reel sliding feeder rack. Even with high speed assembly machines placing in excess of 40000 components per hour (cph), process improvements are possible by increasing the efficiency of the planned placement sequence. This heuristic is developed to identify an improved component placement sequence in a reasonable computation time to allow for future implementation of the methodology in applied situations where time constraints are unavoidable.

Electroplating is a major process in the manufacturing of printed circuit boards. Scheduling the movement of material handling hoists for electroplating processes is generally known as the Hoist Scheduling Problem (HSP) and has been proven to be NP-complete. The objective of HSP is to find a cyclic sequence of hoist moves that maximizes the production throughput. For the past two decades, various optimization and heuristic techniques have been proposed to solve the problem. However, these methods are often limited to the elementary problems. Recently, artificial intelligence (AI) approach using constraint logic programming has been applied to solve the cyclic HSP, but did not consider problems with duplicated process tanks. In this paper, we apply constraint satisfaction to solve HSP with duplicate process tanks. A binary search procedure is proposed and a tighter bound to the cycle length is introduced to reduce the computation effort. The proposed algorithm can be easily implemented on any personal computer with reasonable performance so as to be useful on the shop floor. Finally, we present results for several benchmark examples.

This paper summarizes a study of chip scale packages (CSP) to determine their maximum allowable power dissipation within typical system level environments. These results can be used to determine the applicability of utilizing CSPs from the standpoint of die power dissipation. Both steady state and transient thermal performance is covered in this study. The steady state portion used in-house software, while closed-form solutions were utilized for the transient analysis. The steady state power limit, while governed by a number of parameters, is dependent mainly upon system level parameters (heatsinking, cooling mode — i.e., natural or forced convection, and PCB power loading). Thermal enhancement features (e.g. thermal vias and bumps) are not generally effective in increasing the maximum power that can be dissipated by the package in the end use environment. The variables investigated in the steady state study included die size, thermal vias and bumps, the addition of a heatsink, natural/forced convection boundary conditions, printed circuit board (PCB) heat loading, and PCB thermal conductivity. The transient portion considered die size, pulse shape and duration, and the addition of a heatsink. For relatively short duration transients (e.g. switching an inductive load), the power limit is governed by the die geometry; magnitude, shape and duration of the heating pulse; and the starting and maximum allowable temperatures of the junction.

Electronic packages that are used these days are exposed to different types of vibration loadings in their usage environment. This vibration exposure can be categorized as harmonic and random vibrations. When reliability assessment of modern electronic systems is considered, vibration loading has an important role to play. One of the biggest challenges facing today is the accurate and rapid assessment of fatigue life under the vibration loading. Conventional solder joints were made of lead-tin alloy. According to many environment legislations and rules, lead is prohibited as an ingredient in the solder alloy. The reason for the prohibition of the usage of the lead is that it poisons the environment. In this study, Sn-0.5Cu-3Bi-1Ag is used as the lead-free solder alloy. Fatigue life prediction of electronic package containing SAC405 is conducted with the aid of vibration testing and Finite element analysis under harmonic vibration loading. A specially designed Plastic Ball Grid Array Package (PBGA) component is mounted on Printed Circuit Board (PCB). It is taken as a test vehicle for the vibration test. The test vehicle is excited by a sinusoidal vibration. The frequency of this excitation equals the fundamental frequency of the test vehicle and it is continued till the component fails. Since the solder balls are very small for direct measurement, Finite Element analysis (FEA) is used for noting down the stresses. The stress versus failures cycles (S-N) curve is made by relating both the stresses on the solder balls obtained and the number of failure cycles from vibration analysis. The fatigue life of the component can be estimated from the generated S-N curve. It is analyzed that the methodology is effective in predicting the component’s life. Hence, the reliability of electronic package can be improved.

This paper discusses commonly used reverse engineering methods to illegally recreate printed circuit board (PCB) designs. A solution using transformative electronics is presented to prevent the discussed reverse engineering methods by obfuscating the design. The transformative electronics solution is employed in a specific application that results in a reverse engineered board to be incorrectly recreated, where the signals would be distorted due to added electromagnetic interference (EMI). The nonconductive vias that are part of the obfuscation would allow the inclusion of EMI generators that would not affect the circuit in an original design but would prevent copied designs from working correctly. A machine learning algorithm is being designed to optimize the placement of the EMI sources in an original PCB.

The two prerequisites for the referential-based image comparison method, perfect registration and stable lighting, are hard to achieve under real PCB inspection environment. In this paper, an objection description based on learning for PCB inspection is proposed to compensate for allowable minor variations of object placement and lighting variations, and the threshold image approach is provided to effective avoid false defects. The experimental results show that the developed method is successful in locating defects occurring on PCB, and the result can be used to quality control.

The dynamical model for a drawer structure with multi-layer printed circuit boards (PCBs) was established by the finite element method and the random vibration responses were analyzed in this paper. Firstly, the natural frequencies and their corresponding modes were obtained in terms of the finite element model of the drawer structure with PCBs. Secondly, the random vibration responses were obtained numerically for the drawer structure under random excitations. Finally, sensitive points on each layer of the drawer structure were selected to calculate the vibration responses and the acceleration power spectral density (PSD). The stress power spectral density of typical points on the PCB with high stress was also analyzed. The simulation results reveal that the largest vibration energy of the PCBs usually occurs in the middle layer of the structure and thus components in the middle of the PCBs are most likely to be destroyed.

The INFN group of Rome is developing two silicon microstrip detector planes to be part of the tracking system of the SBS spectrometer, that will be installed in the experimental Hall A of Jefferson Labortatory, in order to improve its resolution. The detector and the PCB design were the results of models simulated using PSPICE. The entire assembly process will be realized in the INFN Roma clean room CL10000 facility.