Narrow Results

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180^∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-$\mu$m CMOS technology with supply voltage of 1.8V. The output clocks with cycle-to-cycle jitter of 2.13ps at 1.6GHz. The phase noise of VCO is $-$137dBc/Hz at an offset of 100MHz and total power consumed by the proposed PLL is 2.63mW at 1.6GHz.

A precharged CMOS high-performance phase frequency detector (PFD) circuit is presented in this paper. The PFD consists of two identical building blocks. Each PFD block generates UP or DOWN signal and consists of $p$- and $n$-precharge stages connected in cascade. The proposed PFD circuit has no feedback path and has zero dead-zone in the phase characteristic, what is important in low jitter applications. It also has minimal blind-zone (extended input detection range) close to the limit imposed by the used CMOS technology. The PFD is designed in 0.13$\mu$m BiCMOS technology and has 1.8V supply voltage. The simulation results of blind-zone values are within the range from $1^{\circ }$ for 1GHz up to $4^{\circ }$ for 8GHz. This circuit can be used in applications for high-frequency and low-power delay locked loop and phase locked loop circuits, effectively.

The paper proposes a CMOS 65 nm 24 GHz wide-band frequency synthesizer with programmability on acquisition speed and supply voltage for low power application in 60 GHz millimeter-wave (mmW) wireless transceiver. The role of mmW phase-locked loop (PLL) is significant for supporting 7 GHz bandwidth across the four channels in IEEE 802.15.3c. The PLL is introduced with consideration of system specifications, as well as the design of individual block. In order to maintain the dynamic behavior of a PLL, two control parameters of its loop transfer function are used for programmability, including the charge pump current and pole-zero position. A regulator is also adopted for supply noise suppression. The Voltage-Controlled Oscillator (VCO) covers frequency range from 24.2 to 29.3 GHz, with 19.1% tuning range. On top of the oscillator, a 1.2 V LDO (Low-Dropout Regulator) with 0.2 V dropout voltage is introduced to increase the immunity against low frequency noise fluctuation from supply. With the proposed structure, the PLL provides a loop bandwidth from 0.94 to 2.05 MHz. The phase margin is larger than 54° and the locking time can be adjusted 16% faster than nominal case. The VCO has better power supply rejection ratio (PSRR) of -48 dB, and Phase Noise of -94 dBc/Hz at 1 MHz frequency offset of 24 GHz.

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ($g_m$) is the main dominant source of frequency and gain ($K_{\mathrm{\text{VCO}}}$) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates $\approx 3$ times variation in $K_{\mathrm{\text{VCO}}}$ across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5GHz is developed in 65nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum $K_{\mathrm{\text{VCO}}}$ variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4mW power from 1V power supply.

A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of $M$-stage ring-VCO with a resolution of $f_{\mathrm{\text{REF}}}∕(k\cdot 2M)$ in a time period of $k\cdot T_{\mathrm{\text{REF}}}$. The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40nm CMOS process and operates from 1.2GHz to 3.6GHz with 8-phase outputs. The total lock time is less than 3$\mu$s including calibration and PLL closed-loop locking processes. Operating at 3.2GHz, the in-band phase noise is better than $-99.4$dBc/Hz and root-mean square (RMS) jitter integrated from 10KHz to 100MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5ps and $-68.5$dBc/Hz, respectively. The clock generator consumes only 3mW from 1.1V supply at high-frequency end and 1.6mW at low-frequency end. The active area is only 0.04mm² including on-chip loop filter and auto-calibration circuits.

DSP (XC2267) is the main control chip which does the increment PI algorithms and realizes the voltage and current double closed-loop control. Three-phase thyristor rectifier method based on the phase self-adjusting of FPGA is proposed. A method for sweptfrequency start circuit is designed to implement the transition between the high-power and low-power. The invert system uses the compound control of improved PWM and frequency phase lock to improve the control accuracy and efficiency. Lastly, by using bench, the circuit is tested and the feasibility and effectiveness of the whole system are verified.