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This work proposes a generalization of the family of chaotic maps without fixed points, proposed by Jafari et al.; 2016 and termed the Vertigo maps. The original map family is parameterized by four control parameters, which can be used to scale the function used as a seed and control its domain. Several theoretical results are provided regarding the existence of the fixed points, the periodic cycles, and the Lyapunov exponents of the maps. Furthermore, two map examples are provided based on the logistic and tent seed functions, which are then studied using a series of numerical tools, like phase portraits, bifurcation diagrams, and Lyapunov exponent diagrams. Finally, an application to a Pseudo-Random Bit Generator is considered. The generator utilizes an exponential-based hash function in combination with the remainder operator.

Dynamical degradation is inevitable when chaotic map is implemented on a device with limited precision. To mitigate the insecurity caused by dynamic degradation, an effective method based on linear feedback and parameter perturbation with previous variables is proposed in this paper. We apply this method on the basis of the most widely used one-dimensional logistic map. Through the numerical experiments, this model is proved to have good chaotic characteristics and strong competitiveness. In addition, in order to verify the practicability of this method, we design a simple process pseudo-random bit generator (PRBG), whose security completely depends on the improved logistic map. The results of NIST experiment show that the generated pseudo-random sequence has ideal randomness.

In this work, the architecture of a dual-coupled linear congruential generator (dual-CLCG) for pseudo-random bit generation is proposed to improve the speed of the generator and minimize power dissipation with the optimum chip area. To improve its performance, a new pseudo-random bit generator (PRBG) employing two-operand modulo adder and without shifting operation-based dual-CLCG architecture is proposed. The novelty of the proposed dual-CLCG architecture is the designing of LCG based on two-operand modulo adder rather than a three-operand one and without using shifting operation as compared to the existing LCG architecture. The aim of the work is to generate pseudo-random bits at a uniform clock rate at the maximum clock frequency and achieve maximum length of the random bit sequence. The power dissipation with the optimum chip area of PRBG is also observed for the proposed architecture. The generated sequence passes all the 15 tests of the National Institute of Standards and Technology (NIST) standard. Verilog HDL code is used for the design of the proposed architecture. Its simulation is done on commercially available Spartan-3E FPGA (ISE Design Suite by Xilinx) as well as on 90-nm CMOS technology (Cadence tool).

A new method for the generation of pseudo-random bits, based on a coupled-linear congruential generator (CLCG) and two multistage variable seeds linear feedback shift registers (LFSRs) is presented. The proposed algorithm dynamically changes the value of the seeds of each linear congruential generator (LCG) by utilizing the multistage variable seeds LFSR. The proposed approach exhibits several advantages over the pseudo-random bit generator (PRBG) methods presented in the literature. It provides low hardware complexity and high-security strength while maintaining the minimum critical path delay. Moreover, this design generates the maximum length of pseudo-random bit sequence with uniform clock latency. Furthermore, to improve the critical path delay, one more architecture of PRBG is proposed in this work. It is based on the combination of coupled modified-LCG with two variable seeds multistage LFSRs. The modified LCG block is designed by the two-operand modulo adder and XOR gate, rather than the three-operands modulo adder and shifting operation, while it maintains the same security strength. The clock gating network (CGN) is also used in this work to minimize the dynamic power dissipation of the overall PRBG architecture. The proposed architectures are implemented using Verilog HDL and further prototyped on commercially available field-programmable gate array (FPGA) devices Virtex-5 and Virtex-7. The realization of the proposed architecture in this FPGA device accomplishes an improved speed of PRBG, which consumes low power with high randomness compared to existing techniques. The generated binary sequence from the proposed algorithms has been verified for randomness tests using NIST statistical test suites.

This paper presents a reconfigurable image confusion scheme, which uses Linear Congruential Generators (LCGs)-based Pseudorandom Bits Generator (PRBG). The PRBG is based on the variable input-coupled LCG with a reconfigurable clock divider. The proposed algorithm encrypts the input image up to four times successively using different random sequences in every attempt. This new scheme aims to efficiently extract statistically strong pseudorandom sequences from a proposed PRBG with a large keyspace and simultaneously increase the security level of the encrypted image. This PRBG was initially designed on Virtex-5 (XC5VLX110T), Virtex-7 (XC7VX330T) and Artix-7 (XC7A100T) Field Programmable Gate Arrays (FPGAs). The statistical properties of the proposed PRBG for four different configurations are verified by the National Institute of Standards and Technology (NIST) tests. Thereafter, a reconfigurable encryption/decryption algorithm that uses the proposed PRBG is developed for secure image encryption. The encryption process was accomplished using the MATLAB tool after obtaining the PRBG keys from the FPGA. To show the quality and strength of the encryption process, security analysis [correlations and Number of Pixels Change Rate (NPCR)] is performed. Security analysis results are compared with the conventional encryption algorithm to show that the developed reconfigurable encryption scheme provides better results in security tests.

A novel multiple-output pseudo-random-bit generator (PRBG) based on a coupled map lattice (CML) consisting of skew tent maps, which generates spatiotemporal chaos, is presented. In order to guarantee PRBG highly effective, avoiding synchronization among the sites in the CML is discussed. The cryptographic properties, such as probability distribution, auto-correlation and cross-correlation, of the PRBG with various parameters, are investigated numerically. The randomness of the PRBG is verified via FIPS 140-2. In addition, as compared with the PRBG based on the CML consisting of the logistic maps, which are often used in chaos-based PRBGs by many other researchers, the ranges of the parameters within which this multiple-output PRBG have good cryptographic properties are much bigger in terms of their cryptographic properties. It lays a foundation for designing a faster and more secure encryption.

A chaotic map which is realized on a computer will suffer dynamical degradation. Here, a coupled chaotic model is proposed to reduce the dynamical degradation. In this model, the state variable of one digital chaotic map is used to control the parameter of the other digital map. This coupled model is universal and can be used for all chaotic maps. In this paper, two coupled models (one is coupled by two logistic maps, the other is coupled by Chebyshev map and Baker map) are performed, and the numerical experiments show that the performances of these two coupled chaotic maps are greatly improved. Furthermore, a simple pseudorandom bit generator (PRBG) based on coupled digital logistic maps is proposed as an application for our method.