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This paper presents the design of a Chirp Spread Spectrum (CSS), ultra-wideband (UWB), pulse generator (PG) and device mismatch impact on its performance. The proposed CSS-PG is built using a differential ring oscillator (RO) controlled by a ramp generator, allowing varying linearly the pulse frequency with time over the CSS pulse duration. Device mismatches and random variations during integrated circuit manufacturing are the most critical imperfections in high precision differential UWB voltage controlled RO circuit. These mismatches lead to behavioral variations of the PG. The proposed CSS-UWB-PG is designed and analyzed using CMOS 0.18$\mu$m technology. The CSS-PG presents an output swing of 266mV Vpp for 20nsec and consumes 1.72mW for a PRF of 10MHz. The simulated PSD covers the UWB low band from 3GHz to 5GHz and complies with the FCC regulations. For $V_{\mathrm{\text{th}}}$ mismatch, the simulation results show a maximum relative accuracy on oscillation frequency and phase noise of 3.43% and 6.9%, respectively. Monte Carlo and process simulation are performed to study the impact of the random parameter variation on this CSS-PG. Theses simulations show the robustness of the proposed design as the PG PSD is still inside the FCC-UWB mask and its bandwidth is greater than 500MHz.

This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation $\sigma /\mu (\%)$ for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation $\sigma /\mu (\%)$ for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry’s production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies.

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16nm MOS-GNRFET model.

The future prospects of complementary metal oxide semiconductor (CMOS) technology are estimated to be replaced by fin-shaped field effect transistor (FinFET) owing to its strong channel control, high driving capability and ease of fabrication. This paper envisages the effects of voltage, temperature and fin variation on power dissipation and delay for static and domino logic circuits. Circuit behavior becomes unpredictable due to process, voltage and temperature (PVT) variations such as irregular power consumption and performance deviation. It also accelerates circuit deterioration and makes them ineffective. The important circuit level leakage power reduction techniques like LCNT, LECTOR and INDEP have been applied to basic gates, 3-bit carry look ahead adder (CLA) and domino logic circuits at 16 nm FinFET technology. It is found that power delay product (PDP) in CLA using INDEP technique exhibits 61.48% less than conventional CLA. Leakage power reduction techniques have also been verified for the footer domino logic (FDL) circuit and performed Monte Carlo simulations for 10000 samples for reliability analysis. INDEP circuits are robust to PVT variations. The simulations have been completed using Cadence Virtuoso tool.