Skip main navigation

Cookies Notification

We use cookies on this site to enhance your user experience. By continuing to browse the site, you consent to the use of our cookies. Learn More
×

System Upgrade on Tue, May 28th, 2024 at 2am (EDT)

Existing users will be able to log into the site and access content. However, E-commerce and registration of new users may not be available for up to 12 hours.
For online purchase, please visit us again. Contact us at customercare@wspc.com for any enquiries.

SEARCH GUIDE  Download Search Tip PDF File

  • articleNo Access

    A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array

    Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

  • articleNo Access

    A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

    This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

  • chapterNo Access

    A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array

    Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

  • chapterNo Access

    A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

    This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.