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This paper focuses on high performance architectures and building blocks for clock and data recovery (CDR) applications. After a review of basic concepts, a parallel CDR architecture for high operation speeds and low-power dissipation is introduced, followed by discussion of linear detectors for multiple octave operation CDR systems. A frequency acquisition architecture, based on standard PLL building blocks, is then presented. Finally, multi-phase and wide-tuning-range oscillators are discussed.

Phase-locked loops (PLL) is a phase and/or frequency tracking system, widely used in communication and control systems. The sinusoidal multiplicative type PLL still remains a recurrent model, due the fact that its derivation is originated from the maximum likelihood approach. In this note, it is showed as a generalized product, called q-product, which can be used to implement the phase detector and improve some important parameters of the PLL system, as the block linearity and pull-in characteristics. Numerical examples are presented in order to illustrate the proposal.

In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched differential pairs. Duty cycle of output differential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6 mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40 mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05 mm² active area in a 0.18 μm CMOS technology.

In this paper, we propose a low-jitter reference-less clock and data recovery (CDR) circuit with a speed range of 9.8–12.5Gb/s. The proposed CDR uses a multi-stage half-rate bang-bang phase detector (ML-HR-BBPD) to maximize the quantization of the phase difference. In addition, a unit interval adjuster (UIA) is added to the CDR circuit. So that the circuit can minimize the phase detector’s phase error before the output clock frequency is locked. Finally, the loop filter (LF) is improved to realize the coarse and fine adjustment of the phase error over a wide range of phase differences. The CDR circuit’s total power consumption is reduced by using a half-rate phase detector. The CDR circuit was fabricated in TSMC 40nm CMOS process. The measured results are obtained in the proposed CDR circuit at a data rate of 12.5Gb/s. With a pseudo-random bit sequence (PRBS) of $2^{31}-1$, the measured result shows that the bit error rate (BER) is $<{10}^{-12}$, and the root mean square jitter recovered in the output is 0.302 ${ps}_{\mathrm{\text{rms}}}$. The circuit’s jitter tolerance (JTOL) is 0.46 UI_pp, and its total power consumption is 74.8mW with a 5.98pJ/bit energy efficiency.

This paper focuses on high performance architectures and building blocks for clock and data recovery (CDR) applications. After a review of basic concepts, a parallel CDR architecture for high operation speeds and low-power dissipation is introduced, followed by discussion of linear detectors for multiple octave operation CDR systems. A frequency acquisition architecture, based on standard PLL building blocks, is then presented. Finally, multi-phase and wide-tuning-range oscillators are discussed.