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The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for implementing practical terahertz systems.

The similarity between unloaded synchronous motor (SM) pull-into-step mechanism and phase locked loop (PLL) synchronization procedure is revealed in this letter. It is shown that both processes possess analogous structure and may therefore be described by same type of equations. As a result, the methodologies used for describing the phase locked loop synchronization may be useful in synchronous motor starting process analysis and vice versa.

A novel 1/4-rate clock phase detector (PD) structure for phase locked loop (PLL)-based clock and data recovery (CDR) is proposed. In this topology, the retimed data is generated within the circuit and no extra circuit is required. Furthermore, the error and reference signals are independent of delay time through gates and thus, no extra replica circuit is needed to compensate such delay. Designed in a 0.18-μm CMOS technology, the proposed 10 Gb/s PD consumes 30 mA from a 1.8 V supply, resulting in a lower power consumption for high-speed applications compared to conventional topologies.

This work presents a fully integrated fractional-$N$ frequency synthesizer that covers the entire frequency bands specified in the IEEE 802.11 a/b/g/n. In this paper, the effects of charge pump (CP) gain mismatch on spectral purity of local oscillator signal is studied theoretically and a new high precision self-calibrated CP is presented for alleviating the nonidealities. The idea is implemented in a 0.18-$\mu$m standard CMOS technology. According to post layout simulation, the proposed calibration circuit demonstrates an excellent matching in the CP currents in a wide voltage range. By using this technique, the average of close-in phase noise of the designed frequency synthesizer is suppressed by more than 12dBc. The active whole chip die area is 0.475mm² and the power dissipation from a 1.8-V DC supply is 17.3–20.6mW.

In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10-MHz crystal oscillator and the design is implemented in a 65-nm CMOS process. The output of the synthesizer has differential quadrature topology and provides the local oscillator signal to a downconverter mixer of C-V2X receiver. Post-layout simulations show that the reference spurs are better than −88dBc through loop sampling technique which was implemented in a 11.8-GHz VCO design for the first time to the best of our knowledge. The best spur level without the loop sampling technique applied is limited to −55dBc. Using the loop sampling technique provides a spur reduction of 33dB which is a significant improvement at this frequency. Based on post-layout simulations, the design has a phase noise of −97/−99/−114dBc for 10kHz/100kHz/1MHz frequency offsets, respectively, which presents competitive numbers with the designs in the literature. The design has 1.2-V nominal supply voltage for the analog and digital blocks. The total power dissipation of the synthesizer core is 6mW from a 1.2-V supply while the output buffers driving a 100-fF load consumes 18mW.

Wideband linearly frequency modulated (LFM) signals are required for many communication navigation applications; however, a limiting factor is the presence of frequency nonlinearity which degrades the system performance significantly. The fluctuations of phase locked loop (PLL) loop gain and voltage controlled oscillator (VCO) gain will results in inconsistent frequency nonlinearity performance in the whole frequency band. In this letter, we propose an effective solution by real-timely tuning the phase/frequency detecting current, along with the iterative compensation algorithm. In this way, the frequency nonlinearity is compensated and a wideband LFM waveform synthesizer can be designed. This approach is validated by experimental results.

Charge pump phase-locked loop(CP PLL) has been widely used in the clocking and data recovery. A high performance design of CP PLL is presented in this paper. It is fabricated in SMIC 0.18μm CMOS process. To reduce noise, the design uses a modified differential charge pump with a large swing, which can effectively inhibit the phase-locked loop output spectrum spurious. A CML oscillator is used, which has lower phase noise and jitter. By changing the difference between the high speed circuit path and low speed circuit path, the delay time of the tuning unit is changed. What’s more, the switched capacitor technology is applied to achieve a wider tuning range. The frequency range of the CP PLL is from 1GHz to 3.1GHz. The phase noise is -107dBc@1MHz and the RMS jitter is 1.725ps at the frequency of 2GHz.

The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for implementing practical terahertz systems.