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A novel phase frequency detector design is introduced in this study, which removes dead and blind zone issues by eliminating reset path, therefore accelerating the acquisition process. High speed, low power and minimal phase noise are all characteristics of the proposed circuit. The circuit is designed in the Cadence Virtuoso environment and is implemented in CMOS GPDK 180 nm library using a 1.8 V supply voltage. Post-layout simulations have been conducted to ensure that the findings are accurate. The circuit’s robustness is tested over process, voltage and temperature fluctuations.

The suggested PFD achieves a phase noise of $-159.17$dBc/Hz, which is significantly lower than other published circuits. This PFD dissipates 10.25$\mu$W of power at its maximum operating frequency of 10 GHz. The PFD encompasses an area of 275$\mu$m². The proposed PFD outperforms other PFD circuits in the literature, making it ideal for applications requiring minimal jitter, low power, etc.

This paper utilizes Taguchi design of experiments and Pareto analysis of variance statistical approaches to demonstrate circuit optimization. The phase-frequency detector (PFD) circuit based on dynamic logic has been chosen for optimization. For various MOSFETs of PFD, three levels and three factors of power supply and width of PMOS and NMOS ($V_{\mathrm{\text{DD}}}$, $w_p$, and $w_n$) are considered to be critical performance governing factors. The Taguchi technique determines the level of significance of a factor that influences a given performance parameter. The crucial factor for a given response is determined via ANOVA analysis. The optimum values for the parameters $V_{\mathrm{\text{DD}}}$, $w_p$, and $w_n$ are likewise determined using this procedure to maximize the circuit’s overall performance. Taguchi DoE and Pareto Anova analyses have been performed using the Minitab software. Simulating the circuit with GPDK 180 nm CMOS technology using these methods ensures that the acquired parameters are correct for best performance. The Cadence Virtuoso tool has been used to conduct pre-layout and post-layout simulations. The simulation outcomes are reasonably close to the ANOVA predicted result. Phase noise, power dissipation, and frequency of operation of the proposed PFD are $-159.56$ dBc/Hz, 9.83 $\mu$W, and 10.21 GHz, respectively, and it occupies a chip area of 300.41 $\mu {\mathrm{\text{m}}}^2$. The proposed PFD is used to implement a charge-pump PLL which performs effectively with a settling time of 2.59 $\mu$s.

A wide range frequency synthesizer is designed with the help of dual voltage tunable Differential Ring Oscillator (DRO). Frequency ranging from 534MHz to 18.56GHz can be generated using the proposed synthesizer. As proposed circuit utilizes dual voltage tunable DRO, a select input is provided to control the output frequency range. Logic low value (0V) of select input generates frequencies from 534MHz to 5.08GHz whereas logic high value (1.1V) of select input enables the frequency generation in the range of 5.08GHz to 18.56GHz. This work utilizes a single charge pump and single loop filter along with charge pump and bias control circuit. Proposed circuit is designed in GPDK 45-nm CMOS technology with supply voltage of 1.1V. Power consumption of the proposed circuits is 2.88mW while generating frequency of 7.84GHz. Proposed synthesizer demonstrates Figure of Merit (FoM2) of $-192.45$dBc/Hz at this frequency. Because of such a wide spectrum, this synthesizer is well suited in the field of satellite communication, GPS and navigation.

The influences of phase noise together with autapse on the resonance dynamics in a modified FitzHugh–Nagumo (FHN) neuron are investigated by numerical simulation, where the neuronal model is in the environment of electromagnetic induction. First, it is found that phase noise can induce double coherence resonances, which is further confirmed to be robust to the feedback gain of induction current. Surprisingly, by individually changing the period of phase noise and the feedback gain, a resonance-like behavior also appears. Subsequently, the significant phenomenon of autapse-induced multiple coherence resonances is discovered. Moreover, the phenomenon of multiple coherence resonances can emerge at a broad parameter range of autaptic strength and autaptic delay.

Through introducing the ingredients of electromagnetic induction and coupled time delay into the original Fitzhugh–Nagumo (FHN) neuronal network, the dynamics of stochastic resonance in a model of modified FHN neuronal network in the environment of phase noise is explored by numerical simulations in this study. On one hand, we demonstrate that the phenomenon of stochastic resonance can appear when the intensity of phase noise is appropriately adjusted, which is further verified to be robust to the edge-added probability of small-world network. Moreover, under the influence of electromagnetic induction, the phase noise-induced resonance response is suppressed, meanwhile, a large noise intensity is required to induce stochastic resonance as the feedback gain of induced current increases. On the other hand, when the coupled time delay is incorporated into this model, the results indicate that the properly tuned time delay can induce multiple stochastic resonances in this neuronal network. However, the phenomenon of multiple stochastic resonances is found to be restrained upon increasing feedback gain of induced current. Surprisingly, by changing the period of phase noise, multiple stochastic resonances can still emerge when the coupled time delay is appropriately tuned to be integer multiples of the period of phase noise.

In this paper, a novel method to realize LC Voltage-Controlled-Oscillator (LC-VCO) operating at 76.2–76.7GHz frequency band for microwave RFIC component is presented. The model of cross-coupled differential LC-VCO is designed in 45nm technology using Complementary Metal Oxide Semiconductor (CMOS) process for Frequency Modulated Carrier Wave (FMCW) automotive radar sensors and RF transceivers application. The impact of VDD, control voltage and temperature variation on frequency shift, phase noise, and output power has been analyzed to optimize the trade-off between frequency, phase noise, and power requirement. The results depict that LC-VCO dissipates 10.45mW power at an operating voltage of 1.5V. The phase noise has been observed to be $-$90dBc/Hz at 1MHz offset at 76GHz carrier frequency. The estimated layout area of IC is $83\times 73\mu$m². The result shows the edge of the design over existing techniques.

This paper presents a new design of low power voltage controlled oscillator (VCO) circuit using three transistors NOR-gate and I-MOS (inversion mode) varactor tuning method. Variation in the oscillation frequency has been obtained by varying the output load capacitance with the use of I-MOS varactor tuning consisting of two PMOS transistors connected in parallel. Variable capacitance across the I-MOS varactor has been achieved by varying the source/drain voltage ($V_{\mathrm{\text{tune}}})$ and back-gate voltage ($V_b)$. Variation of $V_{\mathrm{\text{tune}}}$ from 1V to 2V provides the frequency deviation from 1.970GHz to 1.379GHz with I-MOS width of 8 $\mu$m at power supply voltage ($V_{\mathrm{\text{dd}}})$ of 1.8V. Power consumption of the circuit is 1.296mW with $V_{\mathrm{\text{dd}}}$ of 1.8V. The results have been obtained for different I-MOS varactor widths like 5$\mu$m, 8$\mu$m and 10$\mu$m. Further, variations in the frequency have been obtained from 0.650 GHz to 2.584 GHz with the V_dd variation from 1V to 3V. In addition, by variations of $V_b$ from 0V to 1.8V and $V_{\mathrm{\text{dd}}}$ from 1V to 3V, the proposed oscillators operate in the frequency range from 0.556GHz to 2.584GHz for 8$\mu$m width of I-MOS varactor. Proposed VCO circuit show a phase noise of $-89.779$dBc/Hz at 1MHz offset from the carrier frequency and the figure of merit (FoM) for the VCO is 154.51dB/Hz. Proposed VCO shows an improved performance in terms of power consumption, output frequency and FoM.

To explore the feasibility of physiological manipulation of autaptic structures, the effects of autaptic connections on an FHN-ML neuronal system with phase noise stimulation are studied systematically. Firstly, according to the dynamic analysis of the FHN-ML neuron model, a saddle-node bifurcation can occur on an invariant circle. Under the action of external oscillatory current with phase noise, the neuronal firing activity is sensitive to phase noise with less intensity, and an appropriate noise intensity can induce a significant stochastic resonance phenomenon. Secondly, the chemical autaptic function can effectively regulate the neuronal discharge activity. An inhibitory autapse can not only induce the transition from depolarized resting to periodic spiking, but can also induce the FHN-ML neuron suppressed by strong phase noise to generate a pronounced intermittent high-level burst-like discharge mode when the autaptic conductance is greater than 0.1. Finally, for a two-dimensional regular FHN-ML neuronal network, a small amount of autaptic structures can induce some special waveforms to restore the propagation of nerve impulses interrupted by phase noise disturbance. This indicates the significant regulation of autapses on spatial patterns of the FHN-ML neuronal network. The study can provide some theoretical guidance for building autaptic structures in local areas to modulate the dynamic behaviors of biological neuronal systems.

The high speed quantum-random-number generation based on measuring the quantum phase noise of DFB diode laser is investigated experimentally in this paper. The quantum randomness of the generated random string is physically guaranteed by measuring the random phase fluctuation of laser. The generated random string can pass all the National Institute of Standards and Technology (NIST) tests and the random number generation rate is up to 1.25 Gbps.

Phase noise-induced single coherence resonance (CR) has been reported in previous studies. It is reported here that double CRs can be induced in the FitzHugh–Nagumo (FHN) model by phase noise when the oscillation period of phase noise is much larger than the firing period of the FHN model. By analyzing peaks in the power spectrums for the fast voltage variable and the coefficient variations (CVs) of interspike interval (ISI) series, we find that double CRs corresponding to the frequency of phase noise and the firing frequency of the FHN model respectively appear at small and large noise intensities. This implies that there are double chances for the FHN model to take advantage of the benefits of phase noise. Possible causes of the single CR are also discussed.

Coherent population trapping (CPT) cesium frequency standard plays a significant role in precision guidance of missile and global positioning system (GPS). Low noise 4.596 GHz voltage controlled oscillator (VCO) is an indispensable part of microwave signal source in cesium frequency standard. Low-phase noise is also the most important and difficult performance indicator of VCO. Starting from phase noise analysis method proposed by Leeson, the formulas about the relationship between phase noise of output signal of oscillator feedback model and phase fluctuation spectrum of amplifier, phase noise of oscillator are derived in this paper. Finally, the asymptote model of microwave oscillator is proposed based on the formula derivation. The experiment shows that when the reverse bias voltage of variode is 1.8 V, the designed oscillation frequency of VCO is 4.596 GHz, the power is −1 dBm and the DC power consumption is 19.6 mW. The tendency of phase noise simulation curve and actual test curve conform to asymptote model. The phase noise in 1 and 10 kHz is, respectively, −60.86 and −86.58 dBc/Hz. The significance of the paper lies in determining the main factors influencing oscillator phase noise and providing guiding direction for the design of low-phase noise VCO.

This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of 1.19–4.46GHz for the tuning voltage of 0.3–1.5V. It consumes a low dc power ranging from 2.44mW to 4.79mW for the specified tuning range. The variation of phase noise ranges from $-83.03$dBc/Hz to $-78.65$dBc/Hz at 1MHz offset with the change of tuning voltage as well as tuning frequency. The proposed varactorless VCO has a maximum Figure of Merit (FOM) of $-148.85$dBc/Hz with a differential output power of 1.8dBm at tuning voltage of 0.7V. The elimination of varactor which abates the silicon area consumption and the minimization of the variation of performance parameters are the special outcomes of the proposed active inductor-based VCO. Comparing the performance parameters such as power consumption, FOM and tuning range, the proposed design outperforms most of the cited designs.

A new linear voltage-controlled oscillator (LVCO) implementation using single AD-844 CFA with a pair of AD-835 multiplier devices and a pair of grounded capacitors is proposed. The open-loop transfer function of the topology is analyzed wherein the concept of Short-Circuit Natural Frequency (SCNF) is applied to derive the sinusoid oscillator implementation. The proposed oscillator circuit is then restructured to yield a linear voltage-controlled quadrature oscillator (LVCQO) after appropriate cascade with a CFA-based active integrator. The oscillation frequency is linearly tunable ($f_o\sim 13.2$MHz) by the multiplier control voltage ($V)$. Subsequently, a high-$Q$ selective band-pass (BP) filter is derived. Effects of the CFA port roll-off parameters and its parasitic capacitors ($C_{y,z})$ had been analyzed to be negligible. Measured oscillator response exhibited a THD $\sim 1.8$%, a linearity error ($\mathrm{\Delta })\sim 2.4$% and a phase noise figure of ($-)$104 dBc/Hz at 24-kHz offset.

In this paper, we introduce a unified nonlinear injection locking model of a large class of 1:2 frequency dividers. The model is valid for two-stage dividers, injected with two-phase or single-phase current or voltage sources. We show that this class of dividers can be rigorously analyzed using the theory of planar nonlinear dynamical systems. We provide accurate compact expressions for the locking range, amplitude, frequency and phase noise. The formulas are validated for two types of frequency dividers using simulations.

This paper proposes an improved two-stage and four-stage CMOS ring-Voltage Controlled Oscillator (VCO) design with large frequency at output, improved phase noise, and reduced consumption of power. A PMOS varactor is used in conventional circuit to obtain high tuning-range and very low consumption of power. Cadence Virtuoso 90 nm technology was used to simulate this differential ring-VCO with the proposed dual input differential delay cell. This two-stage and four-stage design gives wider range of tuning from 1.254 to 6.694 GHz (81.26%) and 1.821 to 5.259 GHz (65.37%), respectively, with the change in $V_c$ from 0.1 to 1 V. The power-consumption of two-stage ring VCO and four-stage ring VCO varies from 48.02 to 89.33 $\mu \mathrm{\text{W}}$ and 66.81 to 157.02 $\mu \mathrm{\text{W}}$ respectively. The proposed two-stage and four-stage VCO exhibits −114.46 and −111.06 dBc/Hz at 1 MHz offset from 6.694 and 5.259 GHz carrier frequency, respectively. The proposed two-stage and four-stage differential ring-VCO results in wider tuning range and very low consumption of power and an improved figure of merit and phase-noise.

Bistatic synthetic aperture radar (SAR) operates with distinct transmit and receive antennas that are mounted on separate platforms. Such a spatial separation has several operational advantages, which will increase the capability, reliability and flexibility of future SAR missions. However, this configuration results that there is no cancelation of low frequency oscillator noise as in the monostatic cases. As a consequence, high accurate time synchronization or clock timing jitter compensation must be provided. Literature search reveals little time synchronization work for bistatic SAR has been reported. As such, the use of a new range alignment algorithm to quantify and compensate clock timing jitter is proposed. The impact of clock timing jitter on bistatic SAR is analyzed, and the performance of the proposed algorithm is evaluated. Simulation results show that successful clock timing jitter compensation for bistatic SAR is achieved by using the proposed algorithm.

Noise widely exists in the nervous system, and plays an extremely important role in the information processing of the nervous system, which can enhance or weaken the ability of the nervous system to process information. Nerve cells exist in complex and changeable electromagnetic fields, and their potential changes are significantly regulated by electromagnetic induction. In response to this, first, a memristor is used to simulate the electromagnetic field environment where the nervous system is located, when using different weak periodic signals as the input of the neuron system, the rich stochastic resonance behavior of the FitzHugh–Nagumo neuron system is analyzed under the drive of phase noise. Second, taking the amplitude, period and intensity of phase noise as the main change parameters, and the changes of the parameters of the memristor and the period of the external signal as auxiliary conditions, the stochastic resonance dynamics analysis is carried out from three perspectives: the amplitude and period of phase noise, the amplitude and intensity of phase noise and the intensity and period of phase noise.

This paper proposes a novel readout interface for a high-precision silicon MEMS vibratory gyroscope. The readout interface contains a closed-loop self-resonating driving circuit and a low-noise open-loop capacitance sensing circuit. In order to achieve an overall optimization in noise performance, the noise in driving loop of the interface is analyzed in detail. After the noise optimization, the driving frequency stability achieves 0.93 ppm, the front-end capacitance resolution achieves 0.002 aF/$\sqrt{\mathrm{\text{Hz}}}$. The total zero bias instability achieves 3.82${}^{\circ }$/h, and angle random walk (ARW) achieves 0.014${}^{\circ }$/s/$\sqrt{\mathrm{\text{Hz}}}$.

This paper represents a new enhanced Colpitts oscillator, which is designed based on g_m-boosting of a conventional Colpitts oscillator. The proposed topology increases the negative resistant and enhances the start-up difficulty of the conventional Colpitts oscillator. This enables the Colpitts oscillator to operate in low-power consumption. Moreover, the differential and balanced structure helps limit even-order harmonics and degrades the common mode noise effects in output. The proposed circuit is designed using 0.18 μm technology and is simulated under 1.8 V supply voltage in advanced design system (ADS). Simulations show the output phase noise of -140 dBc/Hz at 1 MHz offset frequency when the operating frequency is 1 GHz.

Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 GHz to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nanoscale CMOS LC oscillators.