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This study is aimed for the analysis of different designs for sensing low magnitude forces which lies in the micro-Newton range and suitable for biomimetic microbotics. For this, a flexible and high sensitive Micro Electro Mechanical System (MEMS) based Force sensor using piezoresistive sensing mechanism has been analyzed. Design analysis is carried out for sensitivity enhancement on microcantilever by incorporating various combinations of stress concentrated regions (SCR) and their respective arrays. The materials under consideration for sensor are polysilicon piezoresistors and Polydimethylsiloxane (PDMS) microcantilever. For design analysis, the designing and simulation work is assessed using Finite Element Analysis approach in COMSOL Multiphysics 5.3a software. The results revealed that the electrical sensitivity of 1.62 mV/$\mu$N within (0–100) $\mu$N operating range is achieved for microcantilever with rectangular SCR with square SCR array. This operating range has many applications in microbotic field such as sensing tactile movements. Hence, MEMS Force sensor for low magnitude forces has been designed with high sensitivity and flexibility.

In this paper, we propose a novel voltage-programmed pixel circuit with polysilicon thin–flim transistors (poly-Si TFTs) for active matrix organic light-emitting diode (AMOLED) displays, which consists of one programming transistor, one driving transistor, four switching transistors and two storage capacitors, respectively. Specifically, the proposed pixel circuit is able to not only efficiently compensate for the threshold variations of TFTs, but also largely suppresses the electrical degradations of the devices caused by the long-term electrical stress. Moreover, the mobility variation of the driving transistor can be compensated as well. The simulation has been performed by HSPICE, and results indicate that the average values of nonuniformities are, respectively, 7.3% as the threshold-voltage varies by $\pm 0.5$V and 2.1%, as the mobility of the driving transistor varies by $\pm 20$%, both of which are much lower than that of the conventional two-transistor and one-capacitor (2T1C) pixel. Furthermore, since the OLED is reverse-biased during the nonemission phases, the lifetime of OLED will be extended naturally. As a consequence, the proposed pixel circuit can substantially improve the display performance.

Polysilicon chemical mechanical planarization (CMP) is an area of research, which has largely been ignored until recently. With the development of bipolar complementary metal oxide semiconductor (BiCMOS), polysilicon has become of increasing importance as the preferred material for filling of deep trench. In this paper, study of removal rates of Polysilicon CMP will be discussed. Traditional models for predicting the polishing rate are typically based on Preston's equation. Here we present a new empirical polishing rate (EPR) model, which is statistically evaluated by cross-validation method, which assess the predictive ability of the model. The study also reveals inadequacies of Preston's equation in describing the polysilicon removal rate in the CMP process.

This paper describes a process technology to make MEMS devices with laterally integrated polysilicon beam as the structural material instead of single crystal silicon for sensors/ actuators. The process consists of fabricating deep silicon trenches, which are then seamlessly filled with the layers of thermal oxide and polysilicon. The polysilicon on the surface is etched back, leaving behind the polysilicon only inside the trenches. The beams are then released by isotropically etching away the silicon surrounding the polysilicon/ silicon oxide structure. This results in free standing polysilicon beams, which form the MEMS structures. The thermal oxide surrounding the polysilicon can be removed by wet HF etch or by isotropic plasma etch. This process can serve as a general platform for realising various types of high aspect ratio MEMS devices. The various stages of the process development, in realising a low stress polysilicon beams and electrical isolation structures are described in the paper.

It is important to investigate the time-dependent deformation of MEMS devices such as thermally driven micro beams because it affect theirs reliability. In this paper, time-dependent buckling of clamped-clamped polysilicon micro beams under high stress and temperature has been modeled by Finite Element Analysis (FEA). A thermo-mechanical, non-linear model has been developed in this analysis. The temperature dependency of polysilicon properties have also been formulated and modeled in this analysis. Depending on input current, two different polysilicon mechanical behaviors, pure elastic buckling and elasto-plastic deformation have been studied. The goal is to consider the changes of elasto-plastic behavior and thermal properties of polysilicon with temperature in this model. The clamped-clamped micro beam of 2μm wide, 2μm thick and 100μ m long is modeled. For buckling phenomenon to occur, this clamped-clamped beam is self-heated by an electrical current input. These micro beams are made of heavily doped polysilicon and are fabricated by surface micro machining technology. The simulation results show the importance of temperature-dependent properties of polysilicon on deflections of micro beams under compressive stress. A comparison is made between the time dependant results obtained from FEA and the experimental results in the literature.

This paper focuses on the problems encountered in the production process of electronic-grade polycrystalline silicon. It points out that the characterization of electronic-grade polycrystalline silicon is mainly concentrated at the macroscopic scale, with relatively less research at the mesoscopic and microscopic scales. Therefore, we utilize the method of physical polishing to obtain polysilicon characterization samples and then the paper utilizes metallographic microscopy, scanning electron microscopy-electron backscatter diffraction technology, and aberration-corrected transmission electron microscopy technology to observe and characterize the interface region between silicon core and matrix in the deposition process of electronic-grade polycrystalline silicon, providing a full-scale characterization of the interface morphology, grain structure, and orientation distribution from macro to micro. Finally, the paper illustrates the current uncertainties regarding polycrystalline silicon.

Large-size electronic-grade polycrystalline silicon is an important material in the semiconductor industry with broad application prospects. However, electronic-grade polycrystalline silicon has extremely high requirements for production technology and currently faces challenges such as carbon impurity breakdown, microstructure and composition nonuniformity and a lack of methods for preparing large-size mirror-like polycrystalline silicon samples. This paper innovatively uses physical methods such as wire cutting, mechanical grinding and ion thinning polishing to prepare large-size polycrystalline silicon samples that are clean, smooth, free from wear and have clear crystal defects. The material was characterized at both macroscopic and microscopic levels using metallographic microscopy, scanning electron microscopy (SEM) with backscattered electron diffraction (EBSD) techniques and scanning transmission electron microscopy (STEM). The crystal structure changes from single crystal silicon core to the surface of the bulk in the large-size polycrystalline silicon samples were revealed, providing a technical basis for optimizing and improving production processes.