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In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal V_DD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V. For designs working under dynamic voltage scaling schemes, our technique presents a very effective and efficient solution for balanced minimum energy operation in the subthreshold region while preserving high performance at the nominal supply voltage.

Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.

The conventional readout of one-transistor–one-capacitor dynamic random-access memories (1T–1C DRAMs) depends on using a sense amplifier to develop the bitline voltage and settle it to the voltage of the power supply, $V_{DD}$, or to 0V depending on whether the stored data is “1” or “0,” respectively. However, using the sense amplifier makes the reading process sluggish. In this paper, a capacitive-voltage divider-based readout scheme is proposed. According to this scheme, the developed bitline voltage is converted into a pulse with a certain starting time. Specifically, this pulse appears at a later time in case of “0” storage than that if a “1” is stored, thus the proposed scheme is aptly called “time-domain readout.” The effects of parameter and component mismatches and technology scaling on the proposed scheme are investigated. The proposed scheme is analyzed quantitatively with a suggestion given to widen the time gap between the starting times of the pulses corresponding to the “0” and “1” states. The proposed scheme is verified by simulation adopting the 45 nm CMOS technology with $V_{DD}=1$V. According to the simulation results, percentage savings of 68.8%, 56.8%, and 32% in the read-access time, the read-cycle time, and the average power-delay product, respectively, are shown. The proposed scheme requires approximately 40% extra area overhead for the reading circuitry. Also, a noise analysis is performed and it is found that the device noise does not affect the proposed scheme significantly.

Process variations have continuously posed significant challenges to the performance and yield of integrated circuits (ICs). The performance modeling and robust optimization method considering process variations has become an important research task in today’s IC design. Aiming at solving the problems of strong nonlinearity and high-dimensional problems in circuit design, this paper proposes a general robust optimization method for ICs by geometric programming. This method first employs regularization sparse models to model a specific performance metric as a posynomial function in terms of design parameters, in order to reduce parameter space dimensionality and to accurately capture the nonlinear relationship between performance perturbations and process variations. Based on the posynomial performance models, this method further uses an uncertainty set to represent the uncertainties of process variations, and formulates the problem of robust optimization under process variations as a general geometric programming model that can be efficiently solved. Experimental results demonstrate that, the proposed method not only enhances the accuracy and efficiency of circuit performance modeling, but also improves the performance yield significantly compared with traditional circuit design methods.

The characterization of interconnect delay metrics in terms of process variations is an important but complicated task for statistical timing analysis in today’s integrated circuits (ICs). This paper presents a stochastic delay characterization framework for multicoupled interconnects in the presence of process variation. The proposed method starts with deriving the stochastic nodal equations for the RLC network that models multicoupled interconnects. By employing polynomial chaos (PC) expansion, a nonsampling-based stochastic prediction method, we further represent the voltage responses of network nodes as a series of orthogonal polynomials of random variables. During the expansion procedure, we use an adaptive approximation algorithm to reduce the number of required sampling points. We then use a stochastic collocation method to estimate the coefficients in the PC expansion model. With the voltage response determined as an expression of a multi-dimensional polynomial of random variables, the stochastic properties of the delay of multicoupled interconnects can be predicted. The proposed method not only takes into account the strong correlations among process variations, but also extracts an explicit delay representation for multicoupled interconnects in terms of process variations. Experimental results demonstrate that the delay characteristics predicted by the proposed method match well with the results by the brute-force Monte-Carlo method. Moreover, a significant speedup over the Monte-Carlo method has been achieved by the proposed delay characterization framework.

Soft errors have always been a concern in the design of digital circuits. As technology down-scales toward Nanometer sizes, emergence of aging effects, process variations, and Multiple Event Transients (METs) has made the soft error rate (SER) estimation of digital circuits very challenging. This paper intends to characterize the challenges by investigating the cross effects of theses issues in overall SER of a circuit. To this regard, we employ a simulation-based SER estimation approach in which the aging effect, process variations and METs are jointly considered in our fault injection process. In our simulation-based SER estimation approach, a statistical gate delay model is used. The fault injection results into ISCAS85 circuit benchmark reveal that the SER estimation without taking into account the aging effects, the process variations, and METs is significantly inaccurate.

In this paper, we propose a high-precision memristive neural network with neurons implemented by complementary metal oxide semiconductor (CMOS) inverters. Regarding the process variations in the memristors and the sensitivity of the memristive crossbar structure to these fluctuations, the read operation with repetitive pulses and feedback-based write in the memristors are used to implement the neural networks trained by the ex-situ method. Moreover, accurate modeling of the neuron circuit (CMOS inverter) and decreasing the mismatch between trained weights and the limited memristances fill the gap between simulation and implementation. To employ physical constraints based on the memristor framework during the training phase, a linear function is utilized to map the trained weights to the acceptable range of memristances after the training phase. To solve the vanishing gradient problem due to the use of the tanh function as an activation function and for better learning of the network, some measures are taken. Moreover, fin field-effect transistor (FinFET) technology is used to prevent the reduction of the accuracy of the inverter-based memristive neural networks due to the process variations. Overall, our implementation improves the speed, area, power-delay product (PDP), and mean square error (MSE) of the training stage by 91.43%, 95.06%, 48.29% and 81.64%, respectively.