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This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.

Quantum confinement in 3-D leads to novel multi-state larger fan-out carrier transport in quantum dot FETs. Single electron transistors (SETs) and quantum cell automata (QCA) devices are limited by the number of carriers in the transport channel, which affects the logic fan-out in sub-5nm integrated circuits. This paper presents several transport channel structures for overcoming this limitation. Layers with large bandgap discontinuities are used to confine carriers along channel length, between source and drain. These layers are formed with low energy gap Ge QDSLs and are used in several two-channel twin-drain n- and p-FETs in SWS configurations: (i) p-FET with coupled SiGe Quantum well (QW) and Ge Quantum Dot Superlattice (QDSL) channel, (ii) n-FET with upper and lower Ge QDSL channels, and (iii) p-FET with upper and lower Ge QDSL channels on n-on-pSi. The coupling of QW and QDSL channels or two Ge QDSL channels, in a spatial wavefunction switched (SWS) FET structure, not only ensures higher concentration of carriers but also multi-state/multi-bit operation. Circuit simulations of 2-bit NOR gate have used BSIM based analog behavioral model (ABM).

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.

Quantum confinement in 3-D leads to novel multi-state larger fan-out carrier transport in quantum dot FETs. Single electron transistors (SETs) and quantum cell automata (QCA) devices are limited by the number of carriers in the transport channel, which affects the logic fan-out in sub-5nm integrated circuits. This paper presents several transport channel structures for overcoming this limitation. Layers with large bandgap discontinuities are used to confine carriers along channel length, between source and drain. These layers are formed with low energy gap Ge QDSLs and are used in several two-channel twin-drain n- and p-FETs in SWS configurations: (i) p-FET with coupled SiGe Quantum well (QW) and Ge Quantum Dot Superlattice (QDSL) channel, (ii) n-FET with upper and lower Ge QDSL channels, and (iii) p-FET with upper and lower Ge QDSL channels on n-on-pSi. The coupling of QW and QDSL channels or two Ge QDSL channels, in a spatial wavefunction switched (SWS) FET structure, not only ensures higher concentration of carriers but also multi-state/multi-bit operation. Circuit simulations of 2-bit NOR gate have used BSIM based analog behavioral model (ABM).