Narrow Results

Recently, the Internet of Things (IOT) has rapidly developed, leading to the development of many smart devices. Moreover, artificial intelligence (AI) and 5G communication are successful, and the demand for high-performance memory is increasing. The emerging nonvolatile RRAM has many advantages, such as low power consumption, fast operation speed, simple structure and excellent scalability, compared with traditional memories; this is promising for complex computing and mass storage. Zinc oxide (ZnO) is a promising candidate for transparent conducting oxide (TCO) applications because of its abundance, high conductivity, low toxicity, and cost-effectiveness. It is currently used in various optoelectronic components including thin-film transistors (TFTs) and photodetectors. Notably, TCO has been increasingly used in the switching layers of random resistive access memory systems. In this paper, we intend to combine AGO with a large energy gap and ZnO with a high conductivity to prepare AGZO as a switching layer for RRAM by co-sputtering. By adjusting the oxygen flow ratio and power of co-sputtering, the AGZO RRAM exhibited high performance with more than 1400 switching cycles, 10²–10³ on/off ratio, and low operation voltage, and high- and low-resistance states could be maintained for more than 10,000s.

Memristive switches are devices which modulate their resistance state depending on the history of the applied current and/or voltage, and have substantial technological potential and as well as scientific interest. In this paper, we review the current state of research on memristive systems. We review the many classes of memristive switching, their physical mechanisms, and their fabrication and operational modes. Next, we discuss the state of the art experimental and modeling/simulation techniques, and the physical insight afforded from these approaches. Finally, we discuss the applications and believed technological potential of these fascinating and exciting devices.

A Ti/ITO structure was used as a point-contact resistive random access memory to simplify the procedures for conventional metal/insulator/metal structures. After the forming process, a ${\mathrm{\text{TiO}}}_x$ interface was formed to fabricate a $\mathrm{\text{Ti}}/{\mathrm{\text{TiO}}}_x/\mathrm{\text{ITO}}$ structure. The $\mathrm{\text{Ti}}/{\mathrm{\text{TiO}}}_x/\mathrm{\text{ITO}}$ structure can be reversibly switched between a high-resistance state and a low-resistance state by using dc voltages at different polarities. The resistive switching was determined by the formation and rupture of oxygen-vacancy filaments. However, the high-forming current resulted in circuit design complexity and reliability concerns. An Ar-plasma treatment was adopted to modify the ITO surface. The Ar-plasma treatment lowered the forming current and improved memory reliability. The Ar-treated sample exhibited an endurance of more than 800 cycles through dc operation and a retention time longer than $10^4\mathrm{\text{s}}$ at $85^{\circ }\mathrm{\text{C}}$, making it suitable for nonvolatile memory applications.

Sneak current issue of RRAM-based crossbar array is one of the biggest hindrances for high-density memory application. The integration of an addition selector to each cell is one of the most familiar solutions to avoid this undesired cross-talk issue, and resistive switching parameters would affect on the storage density. This paper investigates the potential impact of different resistive switching parameters on crossbar arrays with one-diode one-resistor (1D1R) and one-selector one-resistor (1S1R) architectures. Results indicate that 1S1R architecture is a more scalable technology for high-density crossbar array than 1D1R, and the storage density of 1D1R- and 1S1R-based crossbar array shows little dependence on resistance values of high-resistance state and low-resistance state, which gives a guideline for choosing appropriate selectors for RRAM crossbar array with specific parameters.

This paper introduces memristor-based operational amplifiers (OpAmps) in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop OpAmps. An inverting OpAmp, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area.

Memristors can be used to build nonvolatile memory systems with in-memory computing (IMC) capabilities. A number of prior works demonstrate the design of an IMC-capable memory macro using a memristor crossbar. However, read disturbance limits the use of such memory systems built using a 0-transistor, 1-RRAM (0T1R) structure that suffers from the sneak path problem. In this paper, we introduce a scheme for both memory and logic operations using the 1-transistor, 1-RRAM (1T1R) memristor crossbar, which effectively mitigates the read disturbance problem. The memory array is designed using nMOS transistors and the VTEAM memristor model. The peripheral circuitry like decoders, voltage multiplexers, and sense amplifiers is designed using a 45nm CMOS technology node. We introduce a mapping technique to realize arbitrary logic functions using Majority (MAJ) gate operations in the 1T1R crossbar. Through extensive experimentation on benchmark functions, it has been found that the proposed mapping method gives an improvement of 65% or more in terms of the number of time steps required, and 59% or more in terms of energy consumption as compared to some of the recent methods.

The advent of multi-valued logic (MVL) systems provides considerable improvements in energy consumption and computational efficiency compared to binary logic systems. Using resistive random-access memory (RRAM) and carbon nanotube field effect transistors (CNTFETs), this manuscript presents a new design method for ternary logic gates (standard ternary inverter (STI), ternary NOR, and ternary NAND) and some arithmetic circuit applications are implemented based on the proposed ternary logic gates. The simulations of the proposed circuits are carried out in Synopsis HSPICE software by employing 32-nm Stanford CNTFET technology along with the Stanford RRAM model. The robustness of the designed CNTFET-RRAM STI circuit is investigated for variations in process parameters. Simulation results verify that the proposed designs outperform other CNTFET based ternary logic circuits in terms of number of components, power consumption, delay and power delay product (PDP). Furthermore, a reduced change is perceived with respect to power consumption and PDP of the presented logic gates with process deviation, and variations in supply voltage, temperature, capacitance and frequency. The presented STI, TNAND, TNOR, ternary half adder (THA) and ternary multiplier (TMUL) circuits exhibit an improvement in PDP with less transistor count as compared to the other existing designs in the literature.

Based on the first-principles calculation method of density functional theory, the influence of different directions and concentrations of Sn doping on V₂O₅ was discussed. The doping formation energy, electronic density of states, and isosurface charge density of different Sn doping directions and doping concentration structures are calculated. The calculation results of five different crystal orientation doping models show that the doped structure along the [111] crystal orientation has a smaller doping formation energy of 1.879 eV, which has the best electrical properties and the largest charge density. And the charge distribution is the most concentrated. It is most conducive to the formation of conductive filaments. In addition, as the doping concentration increases, the charge density gradually increases. When the doping concentration is 3.174%, the peak impurity energy level is the highest and the band gap is the smallest. At the same time, there is a tendency to form conductive filaments in the direction of charge extension [111], and the resistance change characteristics of vanadium pentoxide are best improved. The research results of this paper can provide certain theoretical guidance for improving the performance of resistive random access memory based on vanadium pentoxide.