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  • articleNo Access

    High Speed FIR Filter Using Radix-2r Multiplier and Its Application for Denoising EOG Signal

    In this paper, a modified finite impulse response (FIR) filter design has been proposed for the denoising bio-electrical signals like Electrooculography(EOG). The proposed filter architecture uses modified multiplier block, which is implemented using modified Radix-2r arithmetic-based representation for minimizing the multiple constant multiplication and conventional ripple carry adders are replaced with 4:2 compressors. This proposed architecture is implemented by using Radix-2r-based multiplier and 4:2 compressor architectures for achieving better improvement in the critical path delay. The Radix-2r-based arithmetic bit recording is used in order to reduce the design complexity of the multiplication. The proposed architecture significantly reduced the delay when compared to existing and conventional architectures.

  • articleNo Access

    Power and Delay Efficient Haar Wavelet Transform for Image Processing Application

    This paper presents a one-level decomposition Haar Discrete Wavelet Transform (DWT) architecture using a 4:2 compressor and carry propagate adder. In Haar DWT architecture, coefficient multiplication is an essential operation. The Haar coefficient multiplication ((xeven±xodd)0.707106) is implemented with Radix2r multiplier and the generated partial products are represented with sign power of two (SPT) terms. The addition of SPT terms is computed with a 4:2 compressor and the final sum is computed with CPA. A Radix2r multiplier with 4:2 compressor technique is used to improve energy and delay. Compared to the previous architectures, the proposed architecture gives reduction in area, power, and delay. The proposed Haar wavelet architecture is implemented in gate-level Verilog HDL and synthesized with UMC 90-nm technology using Cadence RC compiler. When compared to the existing designs, the proposed architecture Haar DWT architecture synthesis results show reduction in latency of 32.32% and 31.46% of circuit area.