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Residue number systems are attractive due to their basic arithmetic operations, such as addition and multiplication, are carry-free; this facilitates low-power, high-speed implementations. But converting from residue to conventional notation is generally problematic. In this paper, we propose a high-speed architecture for reverse conversion; this is based on Base Extension and the Chinese Remainder Theorem.

It is shown that a diminished-1 adder, with minor modifications, can be also used for the modulo 2ⁿ + 1 addition of two n-bit operands in the weighted representation, if the sum of its input operands is decreased by one. This modified diminished-1 adder can perform n-bit modulo 2ⁿ + 1 addition in less area and time than solutions that are based on the use of binary adders and/or weighted modulo 2ⁿ + 1 adders. Therefore, it can be applied effectively to all weighted modulo 2ⁿ + 1 arithmetic components that finally derive two n-bit addends. A small number of weighted arithmetic components have in the past adopted such a scheme without presenting this general theory. By applying this idea, we propose novel multi-operand modulo 2ⁿ + 1 adders (MOMAs) and residue generators (RGs). Experimental results indicate that the resulting arithmetic components offer significant savings in delay, implementation area and average power consumption compared to the currently most efficient solutions.

In this paper, mixed radix conversion (MRC)-based residue number system (RNS)-to-binary converters for two new three-moduli sets {2${}^k-3$, 2${}^k-2$, 2${}^k-1$} and {2${}^k+1$, 2${}^k+2$, 2${}^k+3$} which are derived from the moduli set {2$m+1$, 2$m$, 2$m-1$} are presented. These have the advantage of having one modulus of the form 2${}^k-1$ or 2${}^k+1$ simplifying computations in one residue channel. The proposed reverse converters are evaluated and compared with state-of-the-art reverse converters proposed in literature for other three-moduli sets regarding hardware requirement and conversion time.