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This work investigates the working of an inverter and a ring oscillator using symmetrical junction nonaligned double gate field effect transistors (NADGFETs). The performance of the circuits was investigated with two dielectric (k) materials, i.e., silicon dioxide (low-$k,k=3.9$) and hafnium dioxide (high-$k,k=24$), into the device’s gate oxide. Simulations were performed in the TCAD Sentaurus Sdevice mixed-mode environment, and the circuit’s response is analyzed as a function of supply voltage, load capacitance and temperature. Additionally, this work evaluates the effect of changes in device parameters on the performance of inverter and oscillator configuration. Using the graphical method, the optimal supply voltage of the inverter was determined, with a 0.66V optimal supply, the propagation delay of the inverter with low-k and high-k materials was 6.1ps and 7.5ps, respectively. The inverters’ power delay product with low-k materials is 45.38 aJ and with high-k materials, it is 70.37 aJ. For a better insight into the nonaligned double gate devices’ performance, a 5-stage ring oscillator was simulated. The oscillator circuit gives an output voltage/oscillation frequency of 1.18 V/67 GHz and 1.205V/44 GHz, with low-k and high-k materials, respectively, at 1.0V supply. The oscillator with low-k gate oxide shows a 34.3% increase in oscillation frequency. From the results, it can be concluded that the nonaligned devices with low-k gate oxide will give an improved response in low-power and high-frequency applications.

This paper presents the design of C-CNTFET oscillator's arrays for infrared 'IR' technology. These arrays are contained by both of the LC-tank and the voltage control 'coupled N- and P-type C-CNTFET LC-tank' oscillators. In this paper, the analysis of the impact of CNT diameter variations and the nonlinear capacitances (C_GD and C_GS) were introduced, especially on propagation time, oscillation frequency and power consumption. The C-CNTFET inverter, ring oscillator, LC-tank and coupled N- and P-type C-CNTFET LC-tank oscillator structures were designed and their speeding and performances have been investigated with the proposed n-type of C-CNTFET model supplied by a 0.5 V power voltage. Simulation results show that the n- and p-types LC-tank oscillator circuit designs achieved an approximately equal oscillation frequency, response time and power consumption. Whereas the coupled N- and P-type C-CNTFET LC-tank oscillator has the lowest power consumption equal to 0.13 μW, the highest oscillation frequency (10.08 THz) and the fastest response time (1.81 ps).

This paper deals with design of physical unclonable functions (PUFs) based on field-programmable gate array (FPGA). The goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. Therefore, a design of a ring oscillator (RO)-based PUF producing more output bits from each RO pair is presented. 24 Digilent Basys 2 FPGA boards (Spartan-3E) and 6 Digilent Nexys 3 FPGA boards (Spartan-6) were tested and statistically evaluated indicating suitability of the proposed design for device identification.

A stable PUF output is required for generating cryptographic keys. As post-processing technique to further improve the efficiency of this PUF design, we used Gray code on the obtained bits from RO pairs. Ultimately, the PUF design is combined with error correction code and together with Gray code is able to generate cryptographic keys of sufficient length.

This study presents a two-stage ring voltage-controlled oscillator (VCO) for use in impulse-radio ultra-wideband (IR-UWB) applications. A systematic and efficient graphical optimization method was employed to find the optimal dimensions of the VCO which give a best performance. A good agreement was observed between the desired specifications and simulation results with regard to the optimum component size of the VCO circuit. The operation range of the VCO was extended to cover an ultra-wide tuning range of 176.6%. The phase noise was $-$107.1dBc/Hz at 10MHz offset frequency from a carrier frequency of 4GHz. The power consumption of VCO was 7.41mW from a 1.8V supply voltage. A large tuning range, low power, and appropriate phase noise were obtained with the optimum components size obtained through the optimization method.

This paper presents a low-power, high gain-bandwidth product (GBW) gain cell for gigabits-per-second communications. Based on this gain cell, a large GBW limiting amplifier (LA) and two types of high oscillation-frequency ring oscillators (ROs) are implemented with good energy efficiencies. Fabricated in the 0.18$\mu$m CMOS process, the proposed LA can support 1.25Gbps data-rate with a measured GBW of 338GHz under 5mW. The proposed single- and multi-loop ROs obtain a simulated typical oscillation frequency of 5.26GHz and 6.96GHz, respectively, under 6.2 mW, which is less than one-eighth the power consumption of published ROs at similar frequencies in the same process.

This paper presents a 4GHz low-power ring oscillator with supply and temperature compensation for use in impulse-radio ultra-wideband (IR-UWB) applications. Simulations using TSMC 0.18$\mu$m CMOS technology show that this configuration is able to achieve a 94.87% reduction in the variation of the center frequency of the uncompensated VCO and 25ppm/${}^{\circ }$C temperature stability. Monte Carlo simulations have also been performed, and demonstrate a 3$\sigma$ deviation of about 7.26%. The power for the proposed circuit is only 4.5mW at 27${}^{\circ }$C.

This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit analysis. Post-layout simulation results of the proposed clock generator in 180nm CMOS technology are also presented. It exhibits a wide tuning range of 807 MHz to 2.66 GHz. The phase noise of the output signal is about $-111$dBc/Hz at 10MHz offset frequency. Frequency changes less than $113.06\mathrm{\text{ppm}}{∕}^{\circ }\mathrm{\text{C}}$ in the temperature range of $-40^{\circ }$C–$100^{\circ }$C. The clock generator consumes 0.657mW of power. Results show improvement in comparison to the previous works.

This paper presents a low power temperature compensated CMOS ring oscillator for biomedical applications across a wide temperature range. The proposed circuit deploys an IPTAT (inversely proportional to absolute temperature) bias current by generating an adaptive control voltage in each stage of the oscillator to compensate the overall oscillator’s temperature coefficient (TC). Simulations using TSMC 0.18$\mu$m CMOS technology show that this configuration can achieve a frequency variation less than 0.25%, leading to an average frequency drift of 20.83ppm/^∘C.

Monte Carlo simulations have also been performed and demonstrate a 3$\sigma$ deviation of about 2.15%. The power dissipated by the proposed circuit is only 8.48mW at 25^∘C.

In this paper, we propose an oscillation-type transceiver for wireless chip-to-chip communication (WCC). The proposed transceiver is composed of a ring oscillator, coils, inverter-type amplifier, voltage multiplier and comparator. The ring oscillator itself acts as the on–off keying (OOK) modulator. The envelope of the transferred OOK-modulated signal is detected in the voltage multiplier of the receiver. Given that the proposed transceiver uses an OOK-modulated oscillating signal, the noise immunity is improved compared to the typical pulse-type transceiver. To verify the functionality of the proposed transceiver, we design the transceiver using the 180-nm complementary metal-oxide-semiconductor process. From the measured results, we verify that the proposed transceiver recovers the entered digital signal up to a distance of 0.2mm between the primary and secondary coils. Additionally, the sensitivity to the bias voltage of the latch is nonexistent by virtue of removing the latch in the proposed transceiver.

In this work, reconfigurable Field Effect Transistor (RFET)-based ring oscillator (RO) has been proposed. RFET has two types of gates, control gate and program gate. This work investigates the possibility of exploiting the program gate of the RFET, for frequency tuning and duty cycle control using numerical device simulations. Different frequencies of operations have been demonstrated on the same oscillator by appropriately biasing the program gate. The program gates can also be used to control the duty cycle of the oscillator, at the given frequency. This paper also studies the single event effect (SEE) performance of the proposed RFET-RO. The simulation results suggest that the oscillators working at higher frequency are disturbed less compared to the oscillator working at lower frequency.

This paper presents the design of a Chirp Spread Spectrum (CSS), ultra-wideband (UWB), pulse generator (PG) and device mismatch impact on its performance. The proposed CSS-PG is built using a differential ring oscillator (RO) controlled by a ramp generator, allowing varying linearly the pulse frequency with time over the CSS pulse duration. Device mismatches and random variations during integrated circuit manufacturing are the most critical imperfections in high precision differential UWB voltage controlled RO circuit. These mismatches lead to behavioral variations of the PG. The proposed CSS-UWB-PG is designed and analyzed using CMOS 0.18$\mu$m technology. The CSS-PG presents an output swing of 266mV Vpp for 20nsec and consumes 1.72mW for a PRF of 10MHz. The simulated PSD covers the UWB low band from 3GHz to 5GHz and complies with the FCC regulations. For $V_{\mathrm{\text{th}}}$ mismatch, the simulation results show a maximum relative accuracy on oscillation frequency and phase noise of 3.43% and 6.9%, respectively. Monte Carlo and process simulation are performed to study the impact of the random parameter variation on this CSS-PG. Theses simulations show the robustness of the proposed design as the PG PSD is still inside the FCC-UWB mask and its bandwidth is greater than 500MHz.

In this paper, we introduce a unified nonlinear injection locking model of a large class of 1:2 frequency dividers. The model is valid for two-stage dividers, injected with two-phase or single-phase current or voltage sources. We show that this class of dividers can be rigorously analyzed using the theory of planar nonlinear dynamical systems. We provide accurate compact expressions for the locking range, amplitude, frequency and phase noise. The formulas are validated for two types of frequency dividers using simulations.

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ($g_m$) is the main dominant source of frequency and gain ($K_{\mathrm{\text{VCO}}}$) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates $\approx 3$ times variation in $K_{\mathrm{\text{VCO}}}$ across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5GHz is developed in 65nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum $K_{\mathrm{\text{VCO}}}$ variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4mW power from 1V power supply.

In this study, a chaotic circuit suitable for an integrated circuit is proposed. The circuit consists of two CMOS ring oscillators and a pair of diodes. By using a simplified model of the circuit, the mechanism of generating chaos is explained and the exact solutions are derived. The exact expressions of the Poincaré map and its Jacobian matrix make those possible to confirm the generation of chaos using the Lyapunov exponents and to investigate the related bifurcation phenomena.

The bifurcations of periodic solutions and the generation of chaos in a ring of three unidirectionally coupled linear elements with a single reverse coupling through a piecewise linear function are considered. A discontinuous and a continuous piecewise linear function are employed for the reverse coupling. A chaotic attractor is generated immediately through a Hopf-like boundary equilibrium bifurcation of a focus in both cases. A chaotic attractor is also generated directly through a grazing bifurcation in the case of the discontinuous function, which is replaced with a cascade of period-doubling bifurcations in the case of the continuous function. A chaotic oscillation with the same form is also observed in an experiment on an analog circuit constructed with operational amplifiers. In a smooth version of the system, a ring of three unidirectionally coupled sigmoid neurons with a reverse coupling, the Hopf-like boundary equilibrium bifurcation is replaced with a period-doubling cascade following after the Hopf bifurcation.