Narrow Results

In this work the impact of gate leakage on SRAM is described and two approaches for reducing gate leakage currents are examined in detail. In one approach, the supply voltage is reduced while in the other the potential of the ground node is raised. In both the approaches the effective voltage across SRAM cell is reduced in inactive mode using a dynamic self-controllable switch. Simulation results based on BPTM (Berkeley Predictive Technology Model) for 45 nm channel length device show that the scheme in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node potential is raised. Results obtained show that 96% reduction in the leakage currents of SRAM can be achieved.

This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.