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In-Memory Computing (IMC) is an emerging paradigm that aims to shift computational workload away from CPUs. The bit-serial IMC architecture suffers from larger latency when performing logic and arithmetic operations. In this paper, a general-purpose, energy-efficient Bit Parallel IMC Architecture (BP-IMCA) based on Area-Optimized (AO-8T) static random access memory (SRAM) bit-cell is proposed to perform In-Memory Boolean Logic Computation (IMBC) and Near-Memory Arithmetic (NMA) operations with variable bit-width from 1- to 8-bit. The decoupled read/write paths of the employed AO-8T SRAM bit-cell eliminate compute disturbance during IMBC and NMA operations. A self-terminating read word line decoding scheme is proposed to disconnect the RBL discharging path from GND, which decreases the energy consumption of the proposed IMC architecture by 27.71% at 1V for IMBC operations. In addition to this, a $V_{\mathrm{\text{REF}}}$-based Low-offset Symmetric Differential Sense Amplifier (LSDSA) is proposed to achieve fast and reliable sensing for both normal read and IMBC operations in the proposed IMC architecture. Further, a 4Kb SRAM array is implemented in 65-nm technology to analyze the IMC architecture at a supply voltage of 1V. The operating frequency of 1,355MHz and average energy consumption of 7.04fJ/bit is achieved during logic (IMBC) operations. The 8-bit addition and 8-bit multiplication operations achieve an energy efficiency of 11.1 TOPS/W and 2.28 TOPS/W, respectively, at 1V and 970MHz. Cumulatively, the proposed architecture achieves the lowest figure of merit compared to the state-of-the-art IMC architectures.

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

This paper presents experimental results of nMOS quantum dot gate field effect transistor (QDGFET) based inverter devices for SRAM devices. A three-state inverter device was fabricated and tested with Si/SiO₂ quantum dots. The work performed here builds off previous works performed with Si/SiO₂ dot-based inverters which used two layers of quantum dots. This research explores multi-state SRAM device operation. A three-state (Si QDs) and a four-state (Si and Ge QDs) inverter are described, and they will allow for multistate logic devices to be utilized in everyday logic chips, which will require less devices to perform the same tasks as conventional devices, double the capacity of the device, and require less power, which will generate less of a thermal footprint. The data of the Half Cell SRAM, comprised of one access transistor and an inverter along with a capacitor, is presented here.

This paper investigates the underlying physics of a SRAM device utilizing three-state Quantum Dot Gate (QDG) FETs by building up the physics from the general QDG-FET, its relation to the QDG-Inverter, and ultimately, the QDG-SRAM. The resulting equations from the exploration of the device physics were utilized to create a simulation within SIMULINK. From the simulation, it was found that in addition to being able to store the “1” and “0” states that are customary for an SRAM device, there is also the ability to store an intermediate state and a pseudo-state as a result of the intermediate state, allowing for the possibility of a 2-bit SRAM device in the same spatial constraints of a conventional SRAM unit cell. Additionally, the experimental results of the QDG-SRAM half-cell and the implications of utilizing a 4 state device to create either a 4 state SRAM cell or a 6 state SRAM cell with two pseudo-states are also discussed.

This paper describes fabrication of Quantum Dot Gate n-FETs using SiOx-cladded Si quantum dot self-assembled on the tunnel gate oxide. Experimental I-V characteristics exhibiting 4-states are presented. Simulation is presented for the operation of viable 4-state SRAMs using QDG-FETs.

This paper describes the fabrication of quantum dot gate (QDG) $n$-FETs using GeOx-cladded Ge quantum dot self-assembled on tunnel gate oxide. Experimental I–V characteristics exhibiting 4-states are presented. Simulations are presented for the operation of a viable 8-state SRAM using QDG-FETs.

The design of a 1.7-ns access time prototype CMOS SRAM is presented. The threshold voltages of the wordline-controlled transistors (WCT) of the proposed memory cells are dynamically variable to achieve high-speed and low-power operations. When the cell is in the read or write (R/W) mode, the V_TH of the wordline-controlled transistors is pulled low by increasing the bulk bias such that the drain current will be increased. By contrast, if it is idle in a standby mode, the bulk bias will be reduced by short-circuiting to a ground voltage to subside the leakage current. The highest operating clock rate of the proposed SRAM is measured to be 667 MHz. Moreover, the proposed memory cell possess high stability, the static noise margin is close to 635 mV given the worst case (75°C, FF model, VDD = 1.6 V).

In this paper, we propose a new circuit level hardening techniques that can decrease the sensitivity of Static Random Access Memory (SRAM) cells to radiation induced Single Event Upsets (SEUs). Five different types of 32 nm double gate (DG)-FinFET-based SRAM cells are analyzed. Proposed SRAM cell outperforms over the unhardened SRAM when exposed to radiation. This is primarily due to the modification of the source potential used to reduce the effect of SEU without affecting normal operation. Static Noise Margin (SNM), Read Noise Margin (RNM), Write Noise Margin (WNM) and Power Delay Product (PDP) are the performance metrics computed for each type of SRAM cell. Effect of back gate voltage and back gate oxide thickness variation on device characteristic show detrimental effects on radiation hardened capabilities of a device. Benchmarking is done against DICE latch and it is found that as compared to DICE latch proposed DG-FinFET SRAM has low transistor count, less area, low recovery time and fault tolerance to internal as well as external nodes.

As the supply voltage is reducing with feature size, SRAM cell design is going through severe stability issues. The issue becomes worse due to increased variability in below sub-100 nm technology. In this paper, we present a highly stable 2-port 8T SRAM cell for high speed application in 65 nm technology. The proposed design provides high stability under simultaneous read/write disturbed access without reducing the I_cell. The cell characteristic is extensively examined under random variation. The dynamic read noise margin is improved by 95% over conventional dual port SRAM. The zero-precharge sensing and virtual ground scheme reduce read path leakage current by 95% over conventional high precharge 2-port SRAM cell. The cell current is improved by 52% over conventional design. Finally, an 8 Kb bit-interleaved 2-stage pipelined SRAM architecture is presented using proposed cell. The 2-stage pipeline architecture provides data transfer bandwidth of 3.1 GB/s. Area-efficient 2-stage decoder layout helps to avoid pseudo read problem in unselected cells without sacrificing memory access time.

The stability, leakage power and speed of Static random access memory (SRAM) have become an important issue with CMOS technology scaling. In this paper, a controller circuit is introduced which is separately controlling the load, driver and access transistors of SRAM cell. Based on word line signal value, optimal body bias voltage is generated through control circuitry to control stability, leakage and speed in SRAM cell. The proposed cell gives faster read and writes with an improvement of 68.5% and 89.2% over conventional 6T SRAM cell. In standby mode, about 62.2% leakage power reduction is observed in $8\times 16$ array architecture of SRAM. The proposed cell is implemented with 65nm CMOS technology and exhibits higher hold and write margins with an improvement of 26.29% in hold margin and 16.6% improvement in write margin as compared to conventional 6T SRAM cell. Robustness of the proposed SRAM cell with respect to stability, leakage and speed are confirmed under process, voltage and temperature variations.

Carbon nanotubes (CNTs) provide a better alternative of silicon when it comes to nanoscales. Thanks to the high stability and high performance of carbon nanotube, CNT-based FET (CNTFET) devices are gaining popularity of late. They provide high packaging densities. Not much study had been done to analyze the characteristics of CNTFET SRAM in the presence of single event upset (SEU). The aim of this paper is to analyze the way in which SEU brings alterations in CNTFET SRAM characteristics and perform its comparison with respect to CMOS 6T SRAM. This paper analyzes the impact of SEU on voltage and current characteristics in CNTFET-based SRAM cell during three different conditions —read, write and hold modes. In the analysis, CNTFET SRAM showed that even small amount of radiations can cause flipping in cells and special circuitries are required to detect and correct the errors for SEU affected SRAM.

Leakage power reduction of an SRAM-based look-up table (LUT) in field-programmable gate array (FPGA) has been achieved in this work by implementing an efficient and dynamic power gating technique. The logic of gating is based on the theory of automatically shutting down the power supply to the inactive blocks of LUT during runtime, contrary to all previous works which involved manual intervention for the implementation of power gating. Two techniques of power gating are introduced in this work, PG1 and PG2. PG1 results in more power savings than PG2, however, PG2 has an advantage of low area overhead. Simulation has been carried out for all possible input combinations of LUT, designed in Cadence Virtuoso tool at 45nm technology. The results indicate a leakage power reduction of up to 50% in PG1 technique, with an average area overhead of 14.15%. The power savings in PG2 is up to 38%, with a minimal increase in area of 1.76%. The power bounce noise is also analyzed for the proposed techniques and reported.

In this work, we extend the implementation guidelines of the WDSRAM — Write Driver SRAM — through the definition of a hierarchical implementation model which is applied on the material layout memory design level. This model can be used in order to create WDSRAMs of any size, maintaining the memory’s write function speed-up against the typical SRAM implementation model. The post-layout simulation results are presented in comparison with the corresponding results of the typical SRAM and confirm that the WDSRAM write function speed-up is maintained against the typical SRAM when the memory size increases. A brief background knowledge on the WDSRAM function is also provided.

Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with $m=19$, $n=0$) and Dual chiral value (NCNTFET with $m=19$, $n=0$ and PCNTFET $m=16$, $n=0$) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32nm CNTFET model in HSPICE simulation tool.

A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-$V_{\mathrm{\text{th}}}$ PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ($m,n$). The power and SNM analyses are carried out for $\pm$20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9V to 0.6V and temperature varies from 27^∘C to 125^∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32nm CNTFET model in HSPICE simulation tool.

The design of low power memory cells is the dream of engineers in memory design. A Darlington-based 8T CNTFET SRAM cell is suggested in this paper. It is called the proposed P_CNTFET Darlington 8T SRAM Cell. Compared with that of the traditional 6T and 8T CNTFET SRAM cells, the power and noise performances of the proposed SRAM cell are comparable. Compared to the traditional SRAM cells, the write, hold, read and dynamic power consumption of the proposed cell is much lower. The CNTFET parameters are optimized to boost the noise margin performance of the suggested bit cell. For optimized parameters, the power consumption and SNM of the proposed cell are compared with conventional cells. In contrast to the conventional cells, the HSNM and WSNM of the proposed cell are improved by 6.25% and 66.6%. The proposed cell’s RSNM is 38% greater than the traditional 6T SRAM cell. The proposed cell’s RSNM is 3.33% less than the traditional 8T SRAM cell. MOSFET is also used to implement the proposed SRAM cell and its noise margin and power performance are compared with traditional MOSFET-based SRAM cells. As with the conventional cells, the MOSFET-based implementation of the proposed cell power and SNM performance is also very good. The simulation is done with the HSPICE simulation tool using the Stanford University 32nm CNTFET model.

This paper presents a novel low-leakage 10T SRAM cell along with its new read circuitry. It utilizes isolated read path for the read operation that enhances the read stability of the cell as compared to conventional 6T SRAM cell. The proposed cell has been introduced for IoT applications where low power devices are the primary requirement in order to enhance the battery life. To minimize the leakage current, the PMOS transistor has been employed at the read circuitry which assists to minimize the leakage current due to induced stacking effect. The leakage current is 37.66%, 40.11% and 67.39% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. The read delay for the proposed cell is 39.80%, 89.13% and 42.33% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. Also, the results depict the speed improvement of 48.60%, 52.49% and 55.71% during write “0” and 46.97%, 57.5% and 54.52% improvement during write “1” operation as compared to 6T SRAM, 8T SRAM and RDFC 9T SRAM cells, respectively. The RSNM of the proposed cell is 649 mV that shows enhanced read stability over conventional 6T SRAM cell. The proposed cell proves its robustness against worst-case process variations. All the simulation work has been completed on the Cadence Virtuoso environment at 180 nm technology node.

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ($\mathrm{\text{VDD}}+=1.4$V and $\mathrm{\text{VSS}}-=-0.2$V or 200mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ($\mathrm{\text{VDD}}=1.2$V and $\mathrm{\text{VSS}}=0$V). A $4\times 4$ memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of $4\times 4$ array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.