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This paper addresses the uncertainty that is present in the design of static random access memory (SRAM) cells using an artificial intelligence (AI) technique. The SRAM has much uncertainty in high-performance portable very large-scale integration (VLSI) chips due to their performance and storage density. This paper presents the way for solving the uncertainty problem by evaluating point-by-point recreation derived for the memory cells inform of the power, speed, and area investment funds acquired in the advanced cell configuration when contrasted with the standard regular architecture for autonomous vehicles using AI algorithm. The adiabatic low power technique is implemented to enrich the configuration of the 6T-SRAM cells. The procedure of the adiabatic process will provide high loss in terms of dissipation of energy which is connected to ground (0V) and transition can be converted from ‘1’ to ‘0’. Moreover, this transition will be decreased to a high amount of degree within corresponding memory cells. Thus uncertainties with the AI model can able to deliver low power reduction using the automatic model of operation as standard adiabatic 6T SRAM cells are implemented. To prove the effectiveness in the reduction of uncertainties a low power margin is obtained with marginal values of 0.25 Volts which is much lesser than the existing models.

With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell. Stability has been illustrated with the conventional butterfly method giving read static noise margin (RSNM) and write static noise margin (WSNM) metrics for read stability and write ability, respectively. A comparative analysis with standard six-transistor SRAM cell is carried out. HSPICE simulative analysis has been carried out for 32nm technology node. The redesigned FGMOS SRAM cells provide improved performance. Also, these are robust and reliability efficient with comparable stability.