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This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1V to 1.8V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is $150\mu \mathrm{\text{W}}@1$V and $312\mu \mathrm{\text{W}}@1.8$V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much.

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The quantum adder is an essential attribute of a quantum computer, just as classical adder is needed for operation of a digital computer. We model the quantum full adder as a realistic complex algorithm on a large number of qubits in an Ising spin quantum computer. Our results are an important step toward effective modeling of the quantum modular adder which is needed for Shor's and other quantum algorithms. Our full adder has the following features. (i) The near-resonant transitions with small detunings are completely suppressed, which allows us to decrease errors by several orders of magnitude and to model a 1000-qubit full adder. (We add a 1000-bit number using 2001 spins.) (ii) We construct the full adder gates directly as sequences of radio-frequency pulses, rather than breaking them down into generalized logical gates, such as Control-Not and one qubit gates. This substantially reduces the number of pulses needed to implement the full adder. (The maximum number of pulses required to add one bit (F-gate) is 15.) (iii) Full adder is realized in a homogeneous spin chain. (iv) The phase error is minimized: the F-gates generate approximately the same phase for different states of the superposition. (v) Modeling of the full adder is performed using quantum maps instead of differential equations. This allows us to reduce the calculation time to a reasonable value.