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The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high- and low-threshold buffers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an “in situ reliability assessment” of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high- or low-threshold buffers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

Biomedical applications like body area networks (BAN) necessitate the construction of power optimized SRAMs to enhance the batteries life at BAN nodes. In this work, we have designed a one-sided near-threshold 9TSRAM for low-power portable biomedical applications. The proposed near threshold 9T SRAM (PNT9T SRAM) employs a cross-connected Schmitt trigger (ST) inverter and normal inverter in its cell core. A separate path for reading is also employed to eliminate the reading disturbance. The write disturbance is removed in the PNT9T SRAM by removing the trail from VDD and ground. The write ability is improved with the use of a feedback-cutting approach. The leakage power dissipation of the memory is mitigated by using a tail transistor, virtual ground (VGND). To evaluate the performance, the PNT9T SRAM is compared with conventional 6T (C6T), ST11T, ST9T, TG9T, SBL9T, and SE9T SRAM cells using FinFET 18nm technology at 0.6V power supply. The PNT9T SRAM mitigates the read power, write power, and leakage power by 51.10%, 50.57%, and 78.97%. Furthermore, the read and write static noise margins were improved by 54% and 39.5%, respectively, compared to C6T SRAM.