Narrow Results

The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

We model and apply a stochastic-simulation-based methodology to optimize the machine allocation of a flexible flow shop (FFS) dedicated to integrated circuit (IC) packaging. This contrasts with most previous research on non-deterministic FFS problems wherein stochastic simulation is mostly used to estimate throughput, cycle time, delay cost, or some other measure(s) in order to compare the performances of already-existing heuristic-based algorithms. The methodology applied in this research, called progressive simulation metamodeling for IC Packaging (IC-PSO), while rooted in the traditional metamodeling technique known as Response Surface Methodology (RSM), contrasts with RSM in that it is equipped with well-designed mechanisms to ensure an ever-increasing solution quality in an attempt to achieve the desirable optimality. The computational efficiency that IC-PSO affords IC packaging companies is demonstrated via a numerical study. Meanwhile, an empirical study based on real data was conducted to validate the viability of the proposed methodology in real settings.

Automated material handling systems (AMHS) have been widely used in semiconductor manufacturing. However, the performance of AMHS heavily hinges on vehicle fleet sizing, which is a complex yet crucial problem. For example, a small fleet size may increase the average wait time, but a large fleet size can also result in traffic congestion. This tradeoff is difficult and can be further exacerbated by profound uncertainty in the manufacturing process. In the literature, the existing models are focused on improving the mean-based performance of AMHS, where the resulting optimal vehicle fleet size is fixed, lacking the ability and flexibility to respond to the changes and/or special requirements that suddenly come up in the manufacturing process. Another drawback with the existing models is that they are not able to characterize the upside/downside risks associated with the resulting vehicle fleet size. This paper, motivated by a real project, presents a novel quantile-based decision model to fill the gap. The adjustment of $\alpha$ values in the proposed decision model allows for agile vehicle fleet sizing according to the production situations, resulting in the satisfactory performance of AMHS. We develop a simulation optimization solution method, called ES-AMHS in short, to enable the efficient derivation of the optimal vehicle fleet size. A comprehensive numerical analysis is conducted to evaluate the efficiency and efficacy of the solution method. Finally, an empirical study in cooperation with a wafer fab in Taiwan is presented to show the practical usefulness of this methodology in a real-world setting.

A fuzzy-neural fluctuation smoothing rule is proposed in this study to improve the performance of scheduling jobs with various priorities in a semiconductor manufacturing factory. The fuzzy-neural fluctuation smoothing rule is modified from the well-known fluctuation smoothing rule by improving the accuracy of estimating the remaining cycle time of a job, which is done by applying Chen's fuzzy-neural approach with multiple buckets. To evaluate the effectiveness of the proposed methodology, production simulation is also applied in this study. According to experimental results, incorporating a more accurate remaining cycle time estimation mechanism did improve the scheduling performance especially in reducing the average cycle times. Besides, the fuzzy-neural fluctuation smoothing rule was also shown to be a Pareto optimal solution for scheduling jobs with various priorities in a semiconductor manufacturing factory.

Aristotle’s dictum scio nescio (I know that I don’t know) may serve as a source of enhanced performance for organizations. Awareness of nescience sets the direction for further inquiry, as managers tend to move in the direction that they believe will reduce nescience most. However, nescience is difficult to quantify, so, to date, managers have primarily relied on intuition. This paper introduces a theoretical framework for managing nescience that is based on information theory. This framework is tested in three exploratory empirical studies that take place in highly contrasting settings: semiconductor manufacturing, medical diagnostics and social media analytics. All three studies demonstrate that metrics related to information entropy can be used to quantify nescience. However, practitioners value the framework and its metrics more highly in the settings where the quality of or access to information drives successful product development. The problems encountered in these settings tended to be well-structured, or they were converted from being ill-structured to being well-structured. Further study of more highly contrasting practical settings will be required to determine whether frameworks based on information theory can serve as foundations for a broadly based, pragmatic theory for managing nescience.

This paper presents a new batch machine dispatching policy that incorporates knowledge about future arrivals and the status of critical machines in subsequent (downstream) processing into the batch processing decision process. The intent is to create a methodology that balances the time lots spend waiting at a batch machine with the time spent in setup, thus improving the overall cycle time. Using discrete-event simulation, this heuristic is compared to existing heuristics that do not consider downstream operations to evaluate their impact on the cycle time both for a small three-machine system and a semiconductor manufacturing facility model. The results showed considerable improvement in cycle times for the small three-machine system. Results for the semiconductor-manufacturing model with downstream batching indicate that the new heuristic is robust but produces results consistent with the current standard heuristic; however, with further modifications, this heuristic may be capable of producing significantly better results.

In this paper we present a shifting bottleneck algorithm for scheduling semiconductor testing operations. The algorithm uses global information on the entire state of the shopfloor and a workcenter-based decomposition approach. Workcenters are scheduled one at a time in order of decreasing criticality until a schedule for the entire shop has been developed. The interactions between workcenters are captured using a disjunctive graph representation of the problem. We describe an implementation of two variants of this procedure and compare their performance against that of a number of dispatching rules. Our results show that one of the shifting bottleneck algorithms performs significantly better than all the dispatching rules within reasonable computation times.

We evaluate the performance of several dispatching rules in a semiconductor testing environment and examine the effects of uncertainties in problem data and job arrival patterns. A series of simulation experiments shows that a single dispatching rule seldom performs well for several different performance measures simultaneously, non-homogenous job arrival patterns significantly affect several aspects of system performance while uncertainty in problem data does not, and the choice of dispatching rules for a given performance measure is robust to both arrival patterns and uncertainties.

Semiconductor manufacturing occurs in a highly complex environment where many work areas interact. This paper is motivated by a situation in a test area of semiconductor manufacturing. It concentrates on the operations that occur after the last test insertion. These operations are sometimes referred to as post-test and may be performed by more than one work area. Because post-test operations are the final steps in the manufacturing process they are crucial, and the decisions made when a job reaches these operations greatly impacts on customer satisfaction. For different input variations, common dispatching policies are compared to determine their effects on the system. It was found that input variation significantly affects the output performance. This is consistent with the results in the literature that, in a job-shop environment, job-release policies affect output performance more significantly than dispatching policies. However, dispatching policy effects are still noticeable when input variation is high. Policies that perform well when input variation is high are selected for comparison with a new look-ahead dispatching policy. When compared with the common dispatching policies, in most cases the look-ahead policy performs well for the dual criteria of variance of weekly throughput and percentage of late jobs.

This paper deals with the subsystem of yield management for semiconductor manufacturing. One of the major causes of defects in semiconductor products is the adherence of particles on the wafer, and reduction of such phenomena will be one of the most relevant policies to realize higher yield performance. Aiming to improve the yield of such products, this paper focuses on classifying the types of identification errors for each particle, and analyses the error characteristics of the current particle-monitoring/identification procedure through computer simulation. Further, a revised procedure is proposed to realize better identification performance.

This study aims to calculate the innovativeness index of Lam Research Corporation, a global supplier and one of the largest manufacturers of semiconductor processing equipment since 1980. This study proposes to apply Phan’s innovation measurement framework to Lam Research to estimate its innovativeness index.

The methodology used to construct this framework is a Hierarchical Decision Model (HDM). The HDM used in this research basically divides the problem into three hierarchies—the first level is its mission, i.e., to find the innovativeness index of a company; the second level uses different output criteria contributing to the innovativeness of a company; the third level subcategorizes these output criteria into sub-factors. The HDM uses three expert panels to identify different output criteria contributing to the innovativeness of a company, to evaluate their importance relative to each other, and provide desirability values for each of them. All the experts selected for this study are experienced professionals in the semiconductor industry with different areas of specializations.

Application of this model to Lam Research includes collecting data with respect to all the output factors described in the framework that contribute to the innovativeness of the company, and calculating the score using desirability values and weights estimated by the experts in an innovation measurement framework. The innovativeness index of Lam Research was calculated as 68.96, which is a good score compared to the other companies mentioned in dissertations such as Intel and AMD. Further analysis of these results shows that Lam Research shows strength in Revenue and Market share by new products as well as number of new products introduced every year. However, the highest possible score for Lam Research could have been 73.18 but for data regarding some indicators, such as the number of paper presentations, awards and honors won by Lam Research employees, not being available for evaluation. In addition to this analysis, the innovativeness index of this company can be improved through more publications and patents, and by encouraging a greater number of scientists to conduct researches in different fields of study.

The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

As global competition continues to intensity in high-tech industry such as the semiconductor industry, wafer fabs have been placing more importance on the increase of die yield and the reduction of costs. Because of automatic manufacturing and information integration technologies, a large amount of raw data has been increasingly accumulated from various sources. Mining potentially useful information from such large databases becomes very important for high-tech industry to enhance operational excellence and thus maintain competitive advantages. However, little research has been done on manufacturing data of high-tech industry. Due to the complex fabrication processes, the data integration, system design, and requirement for cooperation among domain experts, IT specialists, and statisticians, the development and deployment of data mining applications is difficult. This chapter aims to describe characteristics of various data mining empirical studies in semiconductor manufacturing, particularly defect diagnosis and yield enhancement. We analyze engineering data and manufacturing data in different cases and discuss specific needs for data preparation in light of different characteristics of these data. This study concludes with several critical success factors for the development of data mining applications in high-tech industry.