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Since crystal structure dictates the resultant physical properties of materials, titled physical features of the P2₁ monoclinic SiGe semiconductors, which are still unclear, have been revealed by density functional theory (DFT). The electronic band gap value with 0.49eV was found to be in the order of previously published cubic and hexagonal closed-packed SiGe semiconductors. Surprisingly, P2₁ monoclinic SiGe has a room temperature Seebeck coefficient of 1500$\mu$V/K which is higher than the reported data of both cubic and hexagonal SiGe alloys. Further, the mechanically stable P2₁ monoclinic phase of the SiGe displays a brittle mechanical character with clear elastic anisotropy has also been deduced. The P2₁ monoclinic phase of the SiGe can be also considered a good high-dielectric material and beneficial for practical applications of IR or UV goals due to its high refractive index.

In this article is presented the new SON process, which key point lies in the transfer of the lattice continuity from a bulk Silicon substrate via a SiGe layer to the Silicon cap layer, both of these layers being obtained by epitaxy. The thin SiGe layer is next removed from underneath the Si cap in an isotropic plasma-assisted chemical dry-etching. The mono-crystalline Si cap layer resulting from this process lies on an air-gap, which gives the name (Silicon On Nothing) to the process. Depending on application, this air-gap may be refilled with a dielectric or with a gate material for double gate applications. In both cases, the thickness of the Si cap as well as that of the air-gap (filled by the dielectric for single gate applications) may be in the range of a few nanometers with a control in the range of the epitaxy process capability. In this article we present the SON process and its implementation to MOSFETs devices and circuits. This development effort converges towards an SON technological platform, allowing easy co-integration of SON and bulk transistors, Gate All Around or multi-gate devices.

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 10²⁰ cm⁻³. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760−825 °C. The results demonstrated that the thermal budget has to be within 780−800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO₂ as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.