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In this paper, we are experimentally demonstrating the multi-bit storage of a nonvolatile memory device with cladded quantum dots as the floating gate. These quantum dot nonvolatile memory (QDNVM) devices were fabricated by using standard complementary metal-oxide-semiconductor (CMOS) process. The quantum dots in the floating gate region assembled using site-specific selfassembly (SSA) technique. Quantum mechanical simulations of this device structure are also presented. The experimental results show that the voltage separation between the bits was 0.15V and the voltage pulses required to write these bits were 11.7V and 30V. These devices demonstrated the larger write voltage separation between the bits.

This paper presents a quantum dot access channel nonvolatile random access memory (QDAC-NVRAM) which has comparable write and erase times to conventional random access memories but consumes less power and has a smaller footprint. We have fabricated long-channel (W/L=15μm/10μm) nonvolatile random access memories (NVRAMs) with 4μs erase times. These devices are CMOS-compatible and employ novel quantum dot access channel (QDAC) which enables fast storage and retrieval of charge from the floating gate layer. In addition, QDNVRAMs are shown to be capable of storing multiple-bits and potentially scalable to sub 22nm. We are also presenting the simulation results. This paper also presents a memory array architecture using QDAC-NVRAMs.

This paper presents a quantum dot access channel nonvolatile random access memory (QDAC-NVRAM) which has comparable write and erase times to conventional random access memories but consumes less power and has a smaller footprint. We have fabricated long-channel (W/L=15µm/10µm) nonvolatile random access memories (NVRAMs) with 4µs erase times. These devices are CMOS-compatible and employ novel quantum dot access channel (QDAC) which enables fast storage and retrieval of charge from the floating gate layer. In addition, QDNVRAMs are shown to be capable of storing multiple-bits and potentially scalable to sub 22nm. We are also presenting the simulation results. This paper also presents a memory array architecture using QDAC-NVRAMs.