Skip main navigation

Cookies Notification

We use cookies on this site to enhance your user experience. By continuing to browse the site, you consent to the use of our cookies. Learn More
×

SEARCH GUIDE  Download Search Tip PDF File

  • articleNo Access

    FPGA IMPLEMENTATION OF HIGH SPEED AND LOW POWER ARCHITECTURES FOR IMAGE SEGMENTATION USING SOBEL OPERATORS

    In this paper we present two architectures for image segmentation using Sobel Operators. The first architecture is designed for optimum speed whereas the second one is designed for low power. To improve the speed of operation and to reduce the memory access two identical processing units operate parallelly. The first architecture is able to segment up to 800 images each of 640 × 480 pixels in one second at 500 MHz clock frequency consuming 27.31 mW dynamic power. The second architecture is able to segment up to 488 images each of 640 × 480 pixels in one second at 300 MHz clock frequency consuming 13.6 mW dynamic power.

  • articleNo Access

    FPGA Implementation of Fuzzy Inference System Based Edge Detection Algorithm

    Edge detection is a very important area in the field of Computer Vision. Edge detectors behave very poorly, their behavior may fall within tolerance in specific situations and have difficulty in adapting to different situations. Human vision is inherently a multiscale phenomenon and is sensitive to orientation and elongation. This work proposes the hardware implementation of efficient fuzzy logic based algorithm, which is used to detect the edges of an image without determining the threshold value. Edge detection in software is not suited for strong real-time applications. This problem is resolved by using hardware implementation on field programmable gate arrays (FPGAs). Fuzzy inference system is developed with four input pixel containing two fuzzy sets (FSs) one for white and another for black and one output pixel containing three FSs for white, black and edge. Fuzzy if-then rules are used to modify the membership functions. Finally, Mamdanidefuzzifier method is used to form the final edge image. For comparison, the same work was implemented using sobel operator. The hardware part is developed by using Verilog language. The FPGA implementation is targeted on Virtex5 Starter kit (xc5vlx50tff1136-1) and Virtex7 starter kit (xc7vx485tffq1157-1) using the updated Xilinx PlanAhead within the ISE 13.4 development suite. The edge thickness can be changed easily by adding new rules or changing output parameters. That is, rule-based approach has flexible structure that can be easily adapted to any time or anywhere and the new fuzzy approach produces better result than sobel operator. Experimental results show the ability and high performance of the proposed algorithm.