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The rapid advancement of semiconductor technology has significantly influenced the development and testing of System-on-a-Chip (SoC) solutions, particularly in the domain of Internet of Things (IoT) automation. This paper reviews the current state of key SoC testing technologies globally, addressing the challenges of integration and the strategies employed to reduce test costs and improve chip reliability. Key technical approaches are examined in three areas: system-level verification, high-speed signal testing, and test optimization. The paper also explores the evolving landscape of SoC design, highlighting unresolved issues of testability and design that affect IoT advancements. As devices and machines become increasingly efficient and compact, SoC platforms must meet specific IoT application requirements. The integration of multiple cores on a single SoC platform shows promise for IoT applications, though it poses challenges in inter-core communication efficiency. Heterogeneous Network-on-Chip Simulators address these challenges by enhancing the interconnectivity within multiprocessor systems. This paper highlights critical aspects of IoT systems, such as power consumption, throughput, and latency, and provides insights into the deployment of SoC solutions in IoT, sensor advancements, and methodological innovations. Future directions in SoC testing and design are discussed, aiming to further the capabilities and applications of SoC in IoT automation. The development and testing of SoC technology represent a paradigm shift from traditional computing systems to more efficient and connected IoT devices. By addressing advanced testing technologies and integration challenges, IoT applications are poised for significant innovation, paving the way toward a smarter, more connected future.

The complexity of System on Chip (SoC) is increasing with the scale of ICs, and Network on Chip (NoC) has become one of the most important solutions for SoC communication. As a significant point of NoC, research of routers and routing algorithms is receiving more and more attention from researchers and research institutes. This paper proposes a high-speed router on-chip router, which adopts wormhole switching mechanism, output queuing caching strategy, Credit-based flow control mechanism and Round-Robin arbitration mechanism, and the entire operation of the router is a two-stage flow. The selection of adaptive and deterministic routing algorithms can be done automatically, and finally, the performance parameters are evaluated.

Physically unclonable functions (PUFs) are an innovative way to generate device unique keys using uncontrollable production tolerances. In this work, we present a method to use PUFs on modern FPGA-based system-on-chips (SoCs). The processor system part of the SoC is used to configure the FPGA part. We propose a reconfigurable PUF design that can be changed by using the partial reconfiguration (PR) feature of modern FPGAs. Multiple ring oscillator PUF (RO PUF) designs are loaded on the same logic blocks of the FPGA in order to make use of different resources, i.e., sources of entropy, on the FPGA. Their frequencies are read out individually and the differences between neighbored oscillators are used to generate a bit response. The responses of each design can be concatenated to a larger response vector that can be used to generate a cryptographic key. We present an implementation that is able to decrease the needed resources by 87.5% on a Xilinx Zynq.

Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.

We propose a safety-oriented design process for IP-based safety-critical system-on-chip (SoC). The proposed safety process can facilitate the measurement of the robustness based on the safety-related metrics and scales of failure-induced risks in a system that can be employed to locate the critical components for protection to effectively diminish the influence of failures on the system. The risk reduction phase is activated to enhance the robustness of critical components identified by vulnerability analysis if the measured robustness is insufficient. An SoC-level safety design platform was built on the SystemC Synopsys Platform Architect MCO to demonstrate the core idea of the safety process. The safety-oriented design process for an ARM-embedded SoC modeled at the TLM level was conducted to demonstrate the feasibility of our safety approach.

Battery Management System (BMS) functions to monitor individual cell in a battery pack and its crucial task is to maintain stability throughout the battery pack. The BMS is responsible for maintaining the safety of the battery as well as not to harm the user or environment. The parameters that are to be monitored in a battery are Voltage, Current and Temperature. With the collected data, BMS carefully monitors the charging–discharging behavior of the battery particularly in the Lithium-ion (Li-ion) batteries in which charging and discharging behavior are completely different. This paper proposes a real-time IOT connected deep learning algorithm for estimation of State-of-Charge (SoC) of Li-ion batteries. This paper provides unique objectives and congruence between model-based conventional methods and state-of-the-art deep learning algorithm, specifically Feed Forward Neural Network (FNN) which is nonRecurrent. This paper also highlights the advantages of Internet-of-Things (IoT) connected deep learning algorithm for estimation of State-of-Charge of Li-ion batteries in Hybrid Electric Vehicles (HEVs) and Electric Vehicles (EVs). The major advantage of the proposed method is that the Artificial Intelligence (AI)-based techniques aim to bring the estimation error less than 2% at a low cost and time without the model of the battery, at par with conventional method of Extended Kalman Filter (EKF) which is the best ever practical estimation theory. Another advantage of the proposed method is that in an abnormal condition (i.e., Unsafe Temperature) the IF This Then That (IFTTT) IoT mobile application interfaced with BMS through ThingSpeak cloud, sends a notification alert to the battery expert or to the user prior to an emergency. Finally, the real-time data of the battery parameters are collected through ThingSpeak cloud platform for future research and analysis.

Traditional patent classification schemes, which are mainly based on either IPC or UPC, are too complicated and general to meet the needs of specific industries. The paper proposes a dynamic classification method, the “user demand-driven patent topic classification”, aiming to a specific industry or technology area. In the paper, classification topics of the method are grouped into technical topic, application topic and application-technical mixed topic. Automatic process of the method using machine learning techniques is presented as well. A case study on the technology area of system on a chip (SoC) is conducted using machine learning techniques, validating the feasibility of the method. The experiment results demonstrate that automatic patent topic classification based on the combination of patents' metadata and citation information can obtain perfect performance with a greatly simplified document preprocessing.