Narrow Results

Low-power static random access memory (SRAM) is in high demand for its power-efficient neural network inference engine requirement. However, the SRAM suffers in terms of operation frequency, power consumption and read delay because its leakage current is increasing exponentially. Also, the design of bit-interleaving SRAM cells is highly attracted to the half-select problem. In this paper, a new read delay compensated, and half-select disturb-free write assist (HDFWA) SRAM is proposed. Also, an 8T HDFWA SRAM cell is introduced for operating in the sub-threshold region and attaining a great static noise margin. In SRAM memory, the leakage will slow down the entire read access, and hence there is a requirement of compensation circuitry to speed up the read operation. The proposed design uses a new compensation method using a sensor circuit to speed up the read operation through the identification of leakage current. Also, it uses a power delay product (PDP) reduction circuitry for minimizing the power dissipation of SRAMs. This PDP improves the effectiveness of the read/write operations by providing a higher supply voltage to the accessed cells that permit high-speed access operations. The proposed cell also has the ability to solve the problem of column (row) half-select by optimizing the read static noise margin (RSNM) and write static noise margin (WSNM) individually. Based on the suggested cell, a $4\times 4$ SRAM array is created. Comparing the proposed HDFWA SRAM cell design to the standard 6T cells, there is a 16% gain in RSNM and a 7.85% decrease in leakage power. Also, the mean average power dissipation of the array is decreased by 25.86%, with the area overhead of only 3.18%.

Biomedical applications like body area networks (BAN) necessitate the construction of power optimized SRAMs to enhance the batteries life at BAN nodes. In this work, we have designed a one-sided near-threshold 9TSRAM for low-power portable biomedical applications. The proposed near threshold 9T SRAM (PNT9T SRAM) employs a cross-connected Schmitt trigger (ST) inverter and normal inverter in its cell core. A separate path for reading is also employed to eliminate the reading disturbance. The write disturbance is removed in the PNT9T SRAM by removing the trail from VDD and ground. The write ability is improved with the use of a feedback-cutting approach. The leakage power dissipation of the memory is mitigated by using a tail transistor, virtual ground (VGND). To evaluate the performance, the PNT9T SRAM is compared with conventional 6T (C6T), ST11T, ST9T, TG9T, SBL9T, and SE9T SRAM cells using FinFET 18nm technology at 0.6V power supply. The PNT9T SRAM mitigates the read power, write power, and leakage power by 51.10%, 50.57%, and 78.97%. Furthermore, the read and write static noise margins were improved by 54% and 39.5%, respectively, compared to C6T SRAM.