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We use a two-compartment model, which includes soma and dendrite, to explore how extracellular subthreshold sinusoidal electric fields (EFs) influence the spike coding of an active neuron. By changing the intensity and the frequency of subthreshold EFs, we find that subthreshold EFs indeed affect neuronal coding remarkably within several stimulus frequency windows where the field effects on spike timing are stronger than that on spiking rate. The field effects are maximized at several harmonics of the intrinsic spiking frequency of an active neuron. Our findings implicate the potential resonance mechanism underlying subthreshold field effects. We also discuss how neuronal morphologic properties constrain subthreshold EF effects on spike timing. The morphologic properties are represented by two parameters, g_c and p, where g_c is the internal conductance between soma and dendrite and geometric factor p characterizes the proportion of area occupied by soma. We find that the contribution to field effects from the variation of p is stronger than that from g_c, which suggests that neuronal geometric features play a crucial role in subthreshold field effects. Theoretically, these insights into how subthreshold sinusoidal EFs modulate ongoing neuron behaviors could contribute to uncovering the relevant mechanism of subthreshold sinusoidal EFs effects on neuronal coding. Furthermore, they are useful in rationally designing noninvasive brain stimulation strategies and developing electromagnetic stimulus techniques.

This paper reports an ultra-low power received signal strength indicator (RSSI) for low frequency (LF) wake-up receiver. Topology theory analysis and subthreshold operation are performed to lower power consumption. Each gain stage of the subthreshold limiting amplifier (LA) employs cascade diode-connected loads to obtain high output impedance while maintaining low power. An offset cancelation circuit with different tail currents, which also operates in the subthreshold region, is employed to reduce the DC offset voltage. Unbalanced source-coupled pairs of subthreshold devices adopted in the full-wave rectification are optimized. A 45dB input dynamic range and $a\pm 1$dB indicating error are achieved at 125KHz frequency. The prototype occupies an active area of 0.39$\times$0.28mm using CSMC 0.153-$\mu$m complementary metal-oxide-semiconductor (CMOS) technology. With a 1.8V supply voltage, the overall current consumption is only 6$\mu$A.

This paper proposes a body-biased bootstrapped CMOS driver for subthreshold applications. The proposed driver has been implemented with the same number of transistors as conventional bootstrapped CMOS driver. The performance of the subthreshold bootstrapped CMOS driver has been compared with the conventional bootstrapped CMOS driver. Our results show that the proposed body-biased subthreshold bootstrapped CMOS driver has 37% reduction in delay and 39% reduction in power dissipation compared to conventional bootstrapped CMOS driver. The proposed driver is more suitable to drive large loads compared to the conventional driver and operates better at subthreshold region.

A low-voltage and low-power all-MOSFET voltage reference is presented having most of the transistors working in subthreshold region. The basic beta-multiplier with cascode transistor provides a supply-independent current utilized by the active load circuit to generate an output reference voltage using body biasing. The proposed circuit is simulated using standard SCL 180-nm CMOS technology for the supply voltage ranging from 0.75V to 1.8V. The simulation obtains an average output voltage reference of 450.4mV for the given supply range at room temperature. The minimum power dissipation at room temperature is 54.37nW. The temperature coefficient (TC) of 28.13ppm/^∘C is achieved having the temperature range of $-$10–87^∘C for the minimum operating supply voltage. It has the PSRR values of $-$39.4dB at 100Hz and $-$12dB at 1MHz. Also, the active area of the proposed circuit is 0.014mm².

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the $I_{\mathrm{\text{on}}}/I_{\mathrm{\text{off}}}$ ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

We introduce a clear constructive methodology of approximation and synthesis of analog functions using the transfer characteristics of the basic differential pair. The new methodology provides circuit designers with an easy-to-understand solution of the function approximation problem employing MOSFETs in weak inversion. It further provides compact formulas for the optimal coefficients involved in the approximation. We confirm the design methodology using SPICE through two examples involving the exponential function.

This paper proposes an all MOSFET transistor-based voltage reference with ultra-low power consumption and high PSRR for Internet of Things applications. The reference voltage is computed using the gate source voltages of the five NMOS transistors, excluding the use of any transistors with high threshold voltages. To provide a steady clamping voltage for the current source, a supply voltage stability circuit with a current source is added which enhances the proposed voltage reference line sensitivity and PSRR. It has been designed and simulated in 0.18$\mu$m CMOS technology to simulate the proposed voltage reference where all MOSFETs function in the subthreshold region with a 0.5V minimum supply voltage. The proposed voltage reference produces a reference voltage of 129.7mV with a supply voltage range of 0.5–3V. Based on simulation results, the proposed voltage reference has an active area of 0.001mm², requires 11.2pW of power and has a line sensitivity of 0.021%/V. For a temperature range of $-$40^∘C to $85^{\circ }$C, the circuit achieves a temperature coefficient of 38.2ppm/^∘C. The power supply rejection ratio of the proposed voltage reference is $-$101.5dB at 10Hz and $-$90dB at 100Hz. The output noise at 100Hz and 1kHz is 4.68and 4.22$\mu$V/$\surd$Hz, respectively.

Crystalline silicon kept at atmospheric pressure was irradiated with 775 nm multiple laser pulses of 150 fs duration at repetition rate 250 Hz. The laser pulses were circularly polarized, with a peak laser fluence of 0.03 J/cm². We observed surface damage at a much lower fluence and lower number of pulses compared to that reported in the literature. Surface damage, cracks and pits formation were observed. The evolution of the surface damage as a function of the number of laser pulses was recorded. The observations were in contrast to the findings in the literature that the silicon surface became structured when irradiated by multiple pulses.