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Conventional circuit breakers suffer from two main deficiencies: they are slow to operate and develop an electrical arc. These may be overcome by using solid-state switches which in turn introduce other problems, most significantly power dissipated while in the on-state. Nevertheless, a number of solid-state devices are candidates for implementation as low-voltage circuit breakers and there are several options based on the semiconductor material that may function as high-power switches. This paper presents a unique, extensive and systematic evaluation of these options. Voltage-controlled devices are selected due to the simplicity of the controlling circuit and their resilience to $dv$/$dt$-induced switching. Properties of fully solid-state circuit breakers are established and systematic comparisons are made among switches built of silicon and other wide bandgap (WBG) devices such as SiC MOS and GaN HEMT transistors. Using SPICE simulation it is shown that solid-state circuit breakers (SSCBs) based on WBG devices exhibit superior characteristics compared with silicon devices, with faster switching and higher voltage and current ratings. Hybrid circuit breakers, combining both conventional and solid-state switches, are discussed too and a new design circuit is simulated and compared to both conventional and fully solid-state designs.

In traditional phased-array T/R modules, front-end modules such as limiter, low-noise amplifier (LNA) and RF switch are generally implemented by independent devices, with low integration and high cost. This paper realizes the integration of all receiver functional modules in the 0.13$\mu$m CMOS SOI process, including RF switch, LNA with limiter, 6-bit digital controlled attenuator and phase shifter, and drive amplifier. The LNA integrates a limiting function, which can suffer 2W continuous wave. Fast charge–discharge circuit is applied to the low insertion loss RF switch, which greatly reduces the switching time. The phase shifter adopts a double balanced switch used for 180^∘ phase shift, which significantly reduces the phase error. The measured channel gain is about 28dB with an NF about 2.3dB and an IP1 dB above $-$14dBm. The state error of attenuator is less than $+∕-0.6$dB with step error less than $+∕-0.3$dB. The RMS phase error of phase shifter is less than 1.8 degrees. The fully integrated transceiver IC occupies an area of $5\times 5.6$mm². This receiver draws only 128mA with a 3.3V power supply.

This paper presents a protocol to support hard real-time traffic of end-to-end communication over non real-time LAN technology. The network is set up with nodes and switches, and real-time communication is handled by software (protocol) added between the Ethernet protocols and the TCP/IP suite. The proposed protocol establishes a virtual circuit based on admission control and manages hard real-time traffic to bypass the TCP/IP stack. This makes considerably reduce the dwell time in the nodes, and increase the achievable data frame rate. After the bypassing, traffic schedule is performed according to dynamic-priority EDF algorithm. The work does not need any modifications in the Ethernet hardware and coexists with TCP/IP suites, and then the LAN with the protocol can be connected to any existing Ethernet networks. It can be adopted in industrial hard real-time applications such as embedded systems, distributed control systems, parallel signal processing and robotics. We have performed some experiments to evaluate the protocol. Compared to some conventional hard real-time network protocols, the proposed one has better real-time performances and meets the requirements of reliability for hard real-time systems.