World Scientific
Skip main navigation

Cookies Notification

We use cookies on this site to enhance your user experience. By continuing to browse the site, you consent to the use of our cookies. Learn More
×

System Upgrade on Tue, May 28th, 2024 at 2am (EDT)

Existing users will be able to log into the site and access content. However, E-commerce and registration of new users may not be available for up to 12 hours.
For online purchase, please visit us again. Contact us at customercare@wspc.com for any enquiries.

A Fully Integrated S-Band Phase-Array Receiver in 0.13 μm CMOS SOI

    https://doi.org/10.1142/S0218126622501419Cited by:0 (Source: Crossref)

    In traditional phased-array T/R modules, front-end modules such as limiter, low-noise amplifier (LNA) and RF switch are generally implemented by independent devices, with low integration and high cost. This paper realizes the integration of all receiver functional modules in the 0.13μm CMOS SOI process, including RF switch, LNA with limiter, 6-bit digital controlled attenuator and phase shifter, and drive amplifier. The LNA integrates a limiting function, which can suffer 2W continuous wave. Fast charge–discharge circuit is applied to the low insertion loss RF switch, which greatly reduces the switching time. The phase shifter adopts a double balanced switch used for 180 phase shift, which significantly reduces the phase error. The measured channel gain is about 28dB with an NF about 2.3dB and an IP1 dB above 14dBm. The state error of attenuator is less than +0.6dB with step error less than +0.3dB. The RMS phase error of phase shifter is less than 1.8 degrees. The fully integrated transceiver IC occupies an area of 5×5.6mm2. This receiver draws only 128mA with a 3.3V power supply.

    This paper was recommended by Regional Editor Giuseppe Ferri.