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This paper proposes an area-efficient CMOS amplifier for neural recording applications. The proposed neural amplifier takes advantage of indirect negative feedback to realize a rather low upper $-$3-dB cutoff frequency. As a result, the capacitance needed to realize the cutoff frequency is so small that can be easily implemented on-chip. Moreover, the proposed circuit also employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. Designed based on a two-stage configuration, the amplifier provides tunable lower cutoff frequency and digitally-programmable upper cutoff frequency and voltage gain. The circuit is designed in a 0.18-$\mu$m technology, and consumes 0.022mm² and 0.27mm² of chip areas for single- and eight-channel designs, respectively. Operated with a supply voltage of 1.8V, power consumption of the proposed amplifier is 36.7$\mu$W with the simulated input-referred noise of 4$\mu {\mathrm{\text{V}}}_{\mathrm{\text{rms}}}$ over 1Hz–10kHz for each channel. The amplifier also provides an output swing of 0.95 V_pp with a total harmonic distortion of $-$50dB at the frequency of 1kHz.

In traditional phased-array T/R modules, front-end modules such as limiter, low-noise amplifier (LNA) and RF switch are generally implemented by independent devices, with low integration and high cost. This paper realizes the integration of all receiver functional modules in the 0.13$\mu$m CMOS SOI process, including RF switch, LNA with limiter, 6-bit digital controlled attenuator and phase shifter, and drive amplifier. The LNA integrates a limiting function, which can suffer 2W continuous wave. Fast charge–discharge circuit is applied to the low insertion loss RF switch, which greatly reduces the switching time. The phase shifter adopts a double balanced switch used for 180^∘ phase shift, which significantly reduces the phase error. The measured channel gain is about 28dB with an NF about 2.3dB and an IP1 dB above $-$14dBm. The state error of attenuator is less than $+∕-0.6$dB with step error less than $+∕-0.3$dB. The RMS phase error of phase shifter is less than 1.8 degrees. The fully integrated transceiver IC occupies an area of $5\times 5.6$mm². This receiver draws only 128mA with a 3.3V power supply.