Journal of Circuits, Systems and Computers

This paper presents a one-level decomposition Haar Discrete Wavelet Transform (DWT) architecture using a 4:2 compressor and carry propagate adder. In Haar DWT architecture, coefficient multiplication is an essential operation. The Haar coefficient multiplication $((x_{\mathrm{\text{even}}}\pm x_{\mathrm{\text{odd}}})\ast 0.707106)$ is implemented with $Radix-2^r$ multiplier and the generated partial products are represented with sign power of two (SPT) terms. The addition of SPT terms is computed with a 4:2 compressor and the final sum is computed with CPA. A $Radix-2^r$ multiplier with 4:2 compressor technique is used to improve energy and delay. Compared to the previous architectures, the proposed architecture gives reduction in area, power, and delay. The proposed Haar wavelet architecture is implemented in gate-level Verilog HDL and synthesized with UMC 90-nm technology using Cadence RC compiler. When compared to the existing designs, the proposed architecture Haar DWT architecture synthesis results show reduction in latency of 32.32% and 31.46% of circuit area.

As an important unit of power management system, traditional analog low-dropout regulator (ALDO) is widely used in System-on-Chip (SoC) design to provide stable and pure power for each sub-circuit block. However, in ultra-low-power design applications, low quiescent current greatly affects the loop gain of ALDO. Digital low-dropout regulator (DLDO) has good low-voltage working ability, process scalability and diversified control schemes, which is more suitable for low-power SoC design. However, a large number of digital circuits with fast switching devices will produce large load current changes, so DLDO needs fast transient response speed to adjust load changes. In recent years, DLDO can be divided into synchronous DLDO and asynchronous DLDO according to different control methods. Among them, the design structure of synchronous DLDO is relatively simple. It depends on an independent global clock, and there is a tradeoff between speed, accuracy and power consumption. When the clock frequency increases, the system needs fast transient response, but the power consumption will increase proportionally, and the current efficiency and loop stability will decrease. Using large output capacitor to deal with load transient is not conducive to improve chip integration. Although asynchronous DLDO can improve the response speed based on the advantages of asynchronous control scheme, the stability of DLDO will face greater risks. Therefore, this paper will introduce several transient response enhancement technologies that do not sacrifice system power consumption, accuracy or stability. It includes adaptive frequency technology and fast response algorithm to improve the transient response speed of synchronous DLDO, event-driven solution and coarse and fine adjustment technology to improve the transient response speed of asynchronous DLDO. On this basis, a typical DLDO structure with excellent performance in the recent 10 years is given.

Modular multiplication (MM) is an important arithmetic operation in public key cryptography (PKC). In this paper, we present the FPGA implementation of the MM using Montgomery MM (MMM) algorithm. The execution performances of this operation depend on the radix-$r$ and the operands length. In fact, when increasing the radix-$r$, the MMM algorithm requires multiplications of digit by operand. On the other hand, when a long modulus is used, the hardware implementation of the MMM needs a large area. Our objective in this work is to realize a scalable architecture able to support any operands length. In order to achieve a best trade-off between computation throughput and hardware resources, our implementation approach is based on the execution of the basic arithmetic operations in serial way. In addition, efficient parallel and pipelined strategies are realized at low-level abstraction for the optimization of the execution time. The implementations results on Virtex-7 circuit show that a 1024-bit MMM runs in 2.09$\mu$s and consumes 581 slices.

The concept based on data mining has drawn considerable attention from various database professionals and research scholars. The progression of computer-based advancements, namely database management and data storage has facilitated the storage of large data and the data mining approaches are employed to gain valuable information from huge databases. Recently, several techniques to association rule mining (ARM) and frequent itemset mining (FIM) have been established; yet the efficiency based on execution time and scalability continues to be seen as a significant limitation that results in poor solution quality. Therefore, it is necessary to enhance the consistency that signifies the total number of frequently discovered frequent itemsets. This paper proposes three different phases namely the pre-processing phase, FIM phase and ARM phase. In the first pre-processing phase, the Twitter databases are pre-processed and converted into a suitable format for FIM. Here, the tweets are converted into related feature sets and items. In the second FIM phase, an improved Apriori algorithm is 1utilized in mining and extracting the frequent Then in the final phase, an adaptive billiard inspired optimization (ABIO) algorithm which is the integration of neural network (NN) optimization algorithm and billiard inspired optimization (BIO) algorithm is proposed for the optimal generation of association rules with minimum support and confidence from the huge itemsets. Finally, the recent tweets based on covidvaccine, BTSlivestreaming, KFC, McDonald’s as well as lockdown achieved using the hashtag is evaluated for various performance measures, like precision, recall, $f$-measure, execution time and memory utilization. Also, comparative analyses are performed to evaluate the efficiency of the proposed technique.

To solve the problem of low accuracy in the traditional FunkSVD recommendation algorithm, an improved FunkSVD algorithm (RM-FS) is proposed. RM-FS is an improvement of the traditional FunkSVD algorithm, using RMSProp, a deep learning optimization algorithm. The RM-FS algorithm can not only solve the problem of reduced accuracy of the traditional FunkSVD algorithm because of iterative oscillations but also alleviate the impact of data sparseness on the accuracy of the algorithm, achieving the effect of improving the accuracy of the traditional algorithm. The experimental results show that the RM-FS algorithm proposed in this paper effectively improves the accuracy of the recommendation algorithm, which is better than the traditional FunkSVD recommendation algorithm and other improved FunkSVD algorithms.

An 11.8-GHz low-power, low phase noise, 65-nm CMOS LC-VCO for V2X communication standards is presented in this work. To achieve low-phase noise performance to fulfill the 5G NR C-V2X standards, several adjustments are made to the conventional LC-VCO topologies. These adjustments are briefly explained in this work. Presented VCO consumes 3.046mA current from a 1.2-V power supply. It has $-$116.13dBc/Hz phase noise at 1MHz offset and tuning range between 11.64GHz and 11.94GHz. A frequency divider circuit is designed and implemented to the presented VCO to satisfy the frequency spectrum of V2X radio access technologies. To the best of authors’ knowledge, this work is the first VCO implemented at 11.8 GHz in a 65-nm CMOS process with the reported phase noise number for 5G NR C-V2X applications.

In traditional phased-array T/R modules, front-end modules such as limiter, low-noise amplifier (LNA) and RF switch are generally implemented by independent devices, with low integration and high cost. This paper realizes the integration of all receiver functional modules in the 0.13$\mu$m CMOS SOI process, including RF switch, LNA with limiter, 6-bit digital controlled attenuator and phase shifter, and drive amplifier. The LNA integrates a limiting function, which can suffer 2W continuous wave. Fast charge–discharge circuit is applied to the low insertion loss RF switch, which greatly reduces the switching time. The phase shifter adopts a double balanced switch used for 180^∘ phase shift, which significantly reduces the phase error. The measured channel gain is about 28dB with an NF about 2.3dB and an IP1 dB above $-$14dBm. The state error of attenuator is less than $+∕-0.6$dB with step error less than $+∕-0.3$dB. The RMS phase error of phase shifter is less than 1.8 degrees. The fully integrated transceiver IC occupies an area of $5\times 5.6$mm². This receiver draws only 128mA with a 3.3V power supply.

This work presents a 7–9GHz in-phase/quadrature (I/Q) direct up-conversion mixer employing a linear voltage-to-current converting baseband input stage for 5G new radio frequency range 2 cellular applications. The proposed baseband stage improves both the large-signal handling capability and small-signal linearity at the input stage of the mixer. The designed double-balanced I/Q up-conversion mixer, which is based on Gilbert-cell mixer, consists of a voltage-to-current converting input stage, switching stages, and an RLC tank. Simulated in a 40-nm CMOS process, the up-conversion mixer achieves a conversion gain of 5dB, input-referred third-order intercept point of 9.6dBm, and input 1-dB gain compression point of –0.8dBm. It draws a DC bias current of 15.8mA from a nominal supply voltage of 1.1V, and the active area is 0.129mm².

In order to solve the problem of environment generalization in continuous state space, an obstacle avoidance method based on region location is proposed. The method is divided into three steps: (1) Using Region Proposal Network (RPN) to localize the obstacle area; (2). The environment map is established by the regional position mapping relation; and (3). The Deep Q-Learning Network (DQN) is used to realize collision detection of the robot, then pixel collision detection module is introduced and finally the pixel collision simulation distance sensor is combined to obtain the distance between the robot and obstacle and whether the collision or not. In this paper, the experiments were carried out in static obstacle environment and in dynamic and static obstacle environment for robot obstacle avoidance tasks. Experimental results show that the problem of environment generalization can be effectively solved by introducing pixel collision detection in the process of robot obstacle avoidance, and the network model trained in a dynamic environment has some generalization ability.

In this paper, we propose a novel multi-scale correlation network (MSCNet) for homography estimation from coarse to fine. First, we extract multi-scale features through a siamese network to generate global and local correlations from feature maps of different scales. Second, we use a group dilated deconvolution block to capture global mapping by increasing the receptive fields in terms of different levels. Third, we employ the channel and spatial attention mechanism to achieve local refinement for small displacements. Finally, we adopt a knowledge distillation strategy to lightweight our model while maintaining relatively high estimation performance. Experimental results on Microsoft Common Objects in Context (MSCOCO) dataset show that our proposed MSCNet outperforms the state-of-the-art approaches in terms of accuracy and parameter count.

In this paper, a power-efficient self write-terminated hybrid full-adder (SWTHFA) has been developed using the self write-terminated write driver and an improved version of the sense amplifier already reported in the literature. The SWTHFA is designed using hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuit based on logic-in-memory architecture. The use of a modified sense amplifier improves the power dissipation and output response on one hand, whereas, on the other hand, self-write-terminated write driver cuts off the unnecessary flow of write current in the driver circuit, thereby eliminates power wastage in SWTHFA. Proposed SWTHFA shows improvement in power saving, output response, read and write power delay product by 38.87%, 26.45%, 40.86% and 36.53%, respectively, compared to conventional write hybrid full-adder (CWHFA). Further, we performed Monte-Carlo simulations by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ to demonstrate the feasibility of SWTHFA in low-power VLSI circuits.

Object detection for aerial images is a crucial and challenging task in the field of computer vision. Previous CNN-based methods face problems related to extreme variation of object scales and the complex background in aerial images, which vary significantly from natural scenes. On the other hand, a great many of existing detectors highly rely on computational performance and cannot handle real-time tasks. To address this problems, we propose a lightweight real-time object detection network which is named VC-YOLO. In the backbone part, we introduce a receptive field extended backbone with limited number of convolution layers to learn the features and context information of various objects. In the detection part, channel attention module and spatial attention module are used to generate discriminative feature representation. To make full use of semantic feature maps in backbone network, we improve the feature pyramid network (FPN) with more lateral connections to reuse the features in each convolution stage. We evaluate VC-YOLO on NWPU VHR-10 and VisDrone benchmark datasets. Experimental results show that VC-YOLO achieves superior detection accuracy with high efficiency compared with the existing methods.

As a requirement of many modern image compression standards faced today, a computational complexity is observed due to the best mode selection in the intra-prediction stage. This computational complexity is tried to be reduced by various techniques without affecting the performance criteria of the image. In this study, a fast search algorithm, which simplifies the mode selection process of the intra-prediction algorithm and provides calculation with less number of modes is proposed. The hardware architecture of this proposed algorithm is implemented for realization. There are two main sections of the intra-prediction algorithm in image compression, namely the image prediction process and the mode selection process. In this study, main objective is to reduce the process time of the mode selection and the simplification of the hardware design. Sum of absolute difference (SAD) is a frequently used criterion to simplify hardware design. The algorithm searches for the most suitable mode in a single step, where the decision is based on the SAD criterion preferred for the simplicity. The proposed algorithm and related hardware architecture is tested by using various experiments. The number of the modes calculated is reduced effectively, while the process is kept within the acceptable limits in terms of peak signal to noise ratio (PSNR) and compression rate (CR) performance criteria. Therefore, the number of clock cycles observed is considerably reduced. The designed architecture is synthesized for the field programmable gate arrays (FPGA) board and the obtained results are given. In addition, these results are compared with the HM reference software where the corresponding results are in accordance with the reference software.

Level-crossing sampling (LCS) is an alternative to the uniform sampling method and is suitable for sparse and bursty signals. LCS, which is adaptive to amplitude variations of the signals, mainly focuses on reducing the total number of samples. Presently, speech signals are sampled with LCS methods that have a constant temporal resolution, and they require time-to-digital converters (TDC) with a wide dynamic range. A long sequence of overflow counts of the TDC counter may be generated during silence regions if the dynamic range is reduced. This paper proposes level-crossing samplers with multiple temporal resolutions for speech signals. Frequency scaling is applied to standard LCS, adaptive LCS and peak sampling. During the silence region, the frequency of the TDC clock is scaled down, which enables the representation of longer intervals with smaller words. The number of bits per sample and hence the total number of samples generated are decreased due to the reduction in the dynamic range of the TDC. Simulation results indicate that the proposed method outperforms the conventional level-crossing samplers, which do not employ frequency scaling. In addition to a significant reduction in data size, this method can also be used for real-time automatic detection of silence regions in a speech signal.

With the rapid development of parallel programming techniques and the widespread use of multiprocessors, scheduling and analysis techniques supporting parallel real-time tasks become a critical topic for multiprocessor real-time systems. Global scheduling that allows the vertices of a parallel task to execute on any processor is a promising scheduling approach with guaranteed theoretical bounds and wide use in practice. However, the complex internal structure of parallel tasks leads to extensive inner- and inter-task interference, which leads to significant pessimism in the worst-case timing analysis. In this paper, a global fixed-priority (G-FP) scheduling with constrained parallelism for parallel real-time tasks based on the sporadic directed acyclic graph (DAG) model is proposed. Each DAG task is assigned a parallel threshold, such that the number of processors occupied by the task is limited to the parallel threshold of the task at a time. We propose a heuristic algorithm to set the parallel threshold and present a response-time analysis (RTA) to exploit the feature of the constrained parallel scheduling. Experiments with randomly generated tasks show that the proposed approach improves the schedulability upon G-FP and federated scheduling in terms of acceptance ratio.

The emergence of computation intensive automotive applications poses significant challenges on computation capacity of automotive electronic systems, thus vehicular edge computing (VEC) is introduced as a new computing paradigm into the internet of vehicle (IoV) to improve its data processing capability. However, as the computation capacity is limited in VEC servers, efficient task offloading algorithms need to be proposed. This paper first proposes a multi-task offloading model and gives the related task response time analysis method, and then, both a mixed-integer linear programming (MILP)-based algorithm and a simulated annealing-based heuristic algorithm are proposed to minimize the task response time. By comparing with a baseline algorithm, the MILP-based offloading algorithm can reduce the average task response time by 91.45%, and the heuristic offloading algorithm can reduce the average task response time by 70%.

The goal of community search across attributed graphs is to locate the community that takes both attribute cohensiveness and constrained structure into account. The keyword closeness of subgraph is usually measured by similarity distance. However, existing works focus on how to find a community that has most relevant to the keywords of the query vertex through the similarity score, whereas we pay more attention to a community that can jointly cover keywords and find subgraph with the maximum core. To address this problem, we propose a novel query keyword-covered group enlargement community search $(KGEC)$. Given an initial subgraph and a set of query keywords, the $KGEC$ search aims to find the community which satisfies the following conditions: (1) it jointly covers all query keywords; (2) it is a subgraph with the maximum core; (3) it is added the minimum vertex set that meets the conditions (1) and (2). We design a baseline enumerateKGEC algorithm ($EGA$), which enumerates all the vertex combinations that cover the remaining query keywords. To further accelerate the search speed, we propose two heuristic algorithms candidate set-based algorithm $(CSBA)$ and candidate set and keyword combination algorithm $(CSKCA)$, which can effectively speed up the search and find a feasible solution. Finally, we evaluate the performance of our algorithms on two real datasets and show effectiveness and efficiency of our algorithms for $KGEC$ problem.

In recent years, automatic mobile robots (AMRs) have been widely concerned in various fields, such as material handling, unmanned aerial vehicle (UAV) cruise, automatic factories and so forth. Compared with traditional robots, an AMR system brings several challenges such as adaptation to the environment, stable communication and robust control. For example, in a complex environment, AMR has to observe the surrounding environment in real time to avoid obstacles, and track the target in real time to change its trajectory until the task is completed, based on an efficient integration of the perception, communication and control. AMR systems require support from various technologies including real-time positioning and navigation, trajectory planning, target tracking, multi-agent systems, robot monitoring and so forth. In order to enable more enhanced applications of AMRs, the geometric adaptability, design characteristics, mobility, flexibility, obstacle avoidance and fault-tolerant control should be further discussed. This paper provides a comprehensive elaboration on the four aspects of AMR systems, namely AMR applications, perception technologies, robot communications and control mechanisms. Future research directions are also pointed out.

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ($\mathrm{\text{VDD}}+=1.4$V and $\mathrm{\text{VSS}}-=-0.2$V or 200mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ($\mathrm{\text{VDD}}=1.2$V and $\mathrm{\text{VSS}}=0$V). A $4\times 4$ memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of $4\times 4$ array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.