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Power and Delay Efficient Haar Wavelet Transform for Image Processing Application

Department of Electronics and Communication Engineering, Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, Krishna 520007, India

E-mail Address: gkishorekumar@vrsiddhartha.ac.in

Corresponding author.

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Mahammad Firose Shaik

Department of Electronics and Instrumentation Engineering, Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, Krishna 520007, India

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Vikram Kulkarni

Department of Information Technology, MPSTME, NMIMS University, Mumbai 400056, India

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, and

Rambabu Busi

Department of Electronics and Instrumentation Engineering, Lakireddy Bali Reddy College of Engineering, Mylavaram, Krishna, Andhra Pradesh 521230, India

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https://doi.org/10.1142/S0218126622200018Cited by:3 (Source: Crossref)

Abstract

This paper presents a one-level decomposition Haar Discrete Wavelet Transform (DWT) architecture using a 4:2 compressor and carry propagate adder. In Haar DWT architecture, coefficient multiplication is an essential operation. The Haar coefficient multiplication $((x_{even} \pm x_{odd}) * 0.707106)$ is implemented with $R a d i x - 2^{r}$ multiplier and the generated partial products are represented with sign power of two (SPT) terms. The addition of SPT terms is computed with a 4:2 compressor and the final sum is computed with CPA. A $R a d i x - 2^{r}$ multiplier with 4:2 compressor technique is used to improve energy and delay. Compared to the previous architectures, the proposed architecture gives reduction in area, power, and delay. The proposed Haar wavelet architecture is implemented in gate-level Verilog HDL and synthesized with UMC 90-nm technology using Cadence RC compiler. When compared to the existing designs, the proposed architecture Haar DWT architecture synthesis results show reduction in latency of 32.32% and 31.46% of circuit area.

This paper was recommended by Regional Editor Emre Salman.

Keywords:

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